XC95144XL High Performance CPLD

0 R XC95144XL High Performance CPLD 0 5 DS056 (v1.5) August 21, 2003 Preliminary Product Specification Features • • • • 5 ns pin-to-pin logic delays System frequency up to 178 MHz 144 macrocells with 3,200 usable gates Available in small footprint packages - 100-pin TQFP (81 user I/O pins) - 144-pin TQFP (117 user I/O pins) - 144-CSP (117 user I/O pins) Optimized for high-performance 3.3V systems - Low power operation - 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals - 3.3V or 2.5V output capability - Advanced 0.35 micron feature size CMOS Fast FLASH™ technology Advanced system features - In-system programmable - Superior pin-locking and routability with Fast CONNECT™ II switch matrix - Extra wide 54-input Function Blocks - Up to 90 product-terms per macrocell with individual product-term allocation - Local clock inversion with three global and one product-term clocks - Individual output enable per output pin with local inversion - Input hysteresis on all user and boundary-scan pin inputs - Bus-hold circuitry on all user pin inputs - Full IEEE Standard 1149.1 boundary-scan (JTAG) Fast concurrent programming Slew rate control on individual outputs Enhanced data security features Excellent quality and reliability - Endurance exceeding 10,000 program/erase cycles - 20 year data retention - ESD protection exceeding 2,000V Pin-compatible with 5V-core XC95144 device in the 100-pin TQFP package Power Estimation Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell in a XC9500XL device may be configured for low-power mode (from the default high-performance mode). In addition, unused product-terms and macrocells are automatically deactivated by the software to further conserve power. For a general estimate of ICC, the following equation may be used: ICC(mA) = MCHS(0.175*PTHS + 0.345) + MCLP(0.052*PTLP + 0.272) + 0.04 * MCTOG(MCHS +MCLP)* f where: MCHS = # macrocells in high-speed configuration PTHS = average number of high-speed product terms per macrocell MCLP = # macrocells in low power configuration PTLP = average number of low power product terms per macrocell f = maximum clock frequency MCTOG = average % of flip-flops toggling per clock (~12%) This calculation was derived from laboratory measurements of an XC9500XL part filled with 16-bit counters and allowing a single output (the LSB) to be enabled. The actual ICC value varies with the design application and should be verified during normal system operation. Figure 1 shows the above estimation in a graphical form. For a more detailed discussion of power consumption in this device, see Xilinx application note XAPP114, “Understanding XC9500XL CPLD Power.” 250 178 MHz 200 Typical ICC (mA) • • • • • • 150 Hi g hP e rfo nc rma e • 104 MHz 100 Low P ow er Description The XC95144XL is a 3.3V CPLD targeted for high-performance, low-voltage applications in leading-edge communications and computing systems. It is comprised of eight 54V18 Function Blocks, providing 3,200 usable gates with propagation delays of 5 ns. See Figure 2 for architecture overview. 50 0 50 100 150 200 Clock Frequency (MHz) DS056_01_121501 Figure 1: Typical ICC vs. Frequency for XC95144XL © 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS056 (v1.5) August 21, 2003 Preliminary Product Specification www.xilinx.com 1-800-255-7778 1 XC95144XL High Performance CPLD R 3 JTAG Port 1 JTAG Controller In-System Programming Controller 54 I/O I/O I/O Fast CONNECT II Switch Matrix I/O 54 18 18 Function Block 1 Macrocells 1 to 18 Function Block 2 Macrocells 1 to 18 I/O Blocks I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR 4 I/O/GTS 54 18 Function Block 3 Macrocells 1 to 18 54 18 Function Block 4 Macrocells 1 to 18 54 18 Function Block 8 Macrocells 1 to 18 DS056_02_101300 Figure 2: XC95144XL Architecture Function Block outputs (indicated by the bold line) drive the I/O Blocks directly. 2 www.xilinx.com 1-800-255-7778 DS056 (v1.5) August 21, 2003 Preliminary Product Specification R XC95144XL High Performance CPLD Absolute Maximum Ratings Symbol VCC VIN VTS TSTG TSOL TJ Description Supply voltage relative to GND Input voltage relative to GND(1) Voltage applied to 3-state output(1) Storage temperature (ambient) Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) Junction temperature Value –0.5 to 4.0 –0.5 to 5.5 –0.5 to 5.5 –65 to +150 +220 +150 Units V V V oC oC oC Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to –2.0 V or overshoot to +7.0V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Recommended Operation Conditions Symbol VCCINT VCCIO VIL VIH VO Parameter Supply voltage for internal logic and input buffers Commercial TA = Industrial TA = 0oC to to 70oC +85oC –40oC Min 3.0 3.0 3.0 2.3 0 2.0 0 Max 3.6 3.6 3.6 2.7 0.80 5.5 VCCIO Units V V V V V V V Supply voltage for output drivers for 3.3V operation Supply voltage for output drivers for 2.5V operation Low-level input voltage High-level input voltage Output voltage Quality and Reliability Characteristics Symbol TDR NPE VESD Data Retention Program/Erase Cycles (Endurance) Electrostatic Discharge (ESD) Parameter Min 20 10,000 2,000 Max Units Years Cycles Volts DC Characteristic Over Recommended Operating Conditions Symbol VOH VOL IIL IIH IIH Parameter Output high voltage for 3.3V outputs Output high voltage for 2.5V outputs Output low voltage for 3.3V outputs Output low voltage for 2.5V outputs Input leakage current I/O high-Z leakage current I/O high-Z leakage current Test Conditions IOH = –4.0 mA IOH = –500 µA IOL = 8.0 mA IOL = 500 µA VCC = Max; VIN = GND or VCC VCC = Max; VIN = GND or VCC VCC = Max; VCCIO = Max; VIN = GND or 3.6V VCC Min < VIN < 5.5V CIN ICC I/O capacitance Operating supply current (low power mode, active) VIN = GND; f = 1.0 MHz VIN = GND, No load; f = 1.0 MHz Min 2.4 90% VCCIO 45 (Typical) Max 0.4 0.4 ±10 ±10 ±10 ±50 10 Units V V V V µA µA µA µA pF mA DS056 (v1.5) August 21, 2003 Preliminary Product Specification www.xilinx.com 1-800-255-7778 3 XC95144XL High Performance CPLD R AC Characteristics XC95144XL-5 Symbol TPD TSU TH TCO fSYSTEM TPSU TPH TPCO TOE TOD TPOE TPOD TAO TPAO TWLH TPLH Parameter I/O to output valid I/O setup time before GCK I/O hold time after GCK GCK to output valid Multiple FB internal operating frequency I/O setup time before p-term clock input I/O hold time after p-term clock input P-term clock output valid GTS to output valid GTS to output disable Product term OE to output enabled Product term OE to output disabled GSR to output valid P-term S/R to output valid GCK pulse width (High or Low) P-term clock pulse width (High or Low) Min 3.7 0 1.7 2.0 2.8 5.0 Max 5.0 3.5 178.6 5.5 4.0 4.0 7.0 7.0 10.0 10.5 XC95144XL-7 Min 4.8 0 1.6 3.2 4.0 6.5 Max 7.5 4.5 125.0 7.7 5.0 5.0 9.5 9.5 12.0 12.6 XC95144XL-10 Min 6.5 0 2.1 4.4 4.5 7.0 Max 10.0 5.8 100.0 10.2 7.0 7.0 11.0 11.0 14.5 15.3 Units ns ns ns ns MHz ns ns ns ns ns ns ns ns ns ns ns VTEST R1 Device Output R2 CL Output Type VCCIO 3.3V 2.5V VTEST 3.3V 2.5V R1 320 Ω 250 Ω R2 360 Ω 660 Ω CL 35 pF 35 pF DS058_03_081500 Figure 3: AC Load Circuit 4 www.xilinx.com 1-800-255-7778 DS056 (v1.5) August 21, 2003 Preliminary Product Specification R XC95144XL High Performance CPLD Internal Timing Parameters XC95144XL-5 Symbol Buffer Delays TIN TGCK TGSR TGTS TOUT TEN Input buffer delay GCK buffer delay GSR buffer delay GTS buffer delay Output buffer delay Output buffer enable/disable delay Product Term Control Delays TPTCK TPTSR TPTTS Product term clock delay Product term set/reset delay Product term 3-state delay 1.6 1.0 5.5 2.4 1.4 7.2 2.7 1.8 7.5 ns ns ns 1.5 1.1 2.0 4.0 2.0 0 2.3 1.5 3.1 5.0 2.5 0 3.5 1.8 4.5 7.0 3.0 0 ns ns ns ns ns ns Parameter Min Max XC95144XL-7 Min Max XC95144XL-10 Min Max Units Internal Register and Combinatorial Delays TPDI TSUI THI TECSU TECHO TCOI TAOI TRAI TLOGI TLOGILP TF Combinatorial logic propagation delay Register setup time Register hold time Register clock enable setup time Register clock enable hold time Register clock to output valid time Register async. S/R to output delay Register async. S/R recover before clock Internal logic delay Internal low power logic delay 2.3 1.4 2.3 1.4 5.0 1.0 5.0 0.5 0.4 6.0 2.6 2.2 2.6 2.2 7.5 1.4 6.4 1.3 0.5 6.4 3.0 3.5 3.0 3.5 10.0 1.8 7.3 1.7 1.0 7.0 ns ns ns ns ns ns ns ns ns ns Feedback Delays Fast CONNECT II feedback delay - 1.9 - 3.5 - 4.2 ns Time Adders TPTA TSLEW Incremental product term allocator delay Slew-rate limited delay 0.7 3.0 0.8 4.0 1.0 4.5 ns ns DS056 (v1.5) August 21, 2003 Preliminary Product Specification www.xilinx.com 1-800-255-7778 5 XC95144XL High Performance CPLD R XC95144XL I/O Pins Function Block 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17(1) 18 1 2(1) 3 4 5(1) 6(1) 7 8(1) 9(1) 10 11 12 13 14 15 16 17 18 TQ100 TQ144 CS144 11 12 13 14 15 16 17 18 19 20 22(1) 99(1) 1(1) 2(1) 3(1) 4(1) 6 7 8 9 10 23 16 17 25 19 20 21 22 31 24 26