HCMOS Microcontroller Unit

Order this document by MC68HC05P18A/D MC68HC05P18A HCMOS Microcontroller Unit TECHNICAL DATA N O N - D I S C L O S U R E A G R E E M E N T HC 5 R E Q U I R E D Technical Data R E Q U I R E D A G R E E M E N T N O N - D I S C L O S U R E Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Technical Data 2 MC68HC05P18A MOTOROLA Technical Data — MC68HC05P18A List of Sections Section 1. General Description . . . . . . . . . . . . . . . . . . . . 15 Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Section 3. Central Processor Unit (CPU) . . . . . . . . . . . . 33 Section 4. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Section 5. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Section 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . 49 Section 7. Input/Output (I/O) Ports . . . . . . . . . . . . . . . . . 55 Section 8. 16-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Section 9. Serial Input/Output Ports (SIOP) . . . . . . . . . . 77 Section 10. EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Section 11. Analog-to-Digital (A/D) Converter . . . . . . . . 91 Section 12. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . 97 Section 13. Electrical Specifications . . . . . . . . . . . . . . . 115 Section 14. Mechanical Specifications . . . . . . . . . . . . . 125 Section 15. Ordering Information . . . . . . . . . . . . . . . . . 127 MC68HC05P18A MOTOROLA List of Sections Technical Data 3 N O N - D I S C L O S U R E A G R E E M E N T R E Q U I R E D List of Sections R E Q U I R E D N O N - D I S C L O S U R E Technical Data 4 List of Sections A G R E E M E N T MC68HC05P18A MOTOROLA Technical Data — MC68HC05P18A Table of Contents Section 1. General Description 1.1 1.2 1.3 1.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Section 2. Memory Map 2.1 2.2 2.3 2.4 2.5 2.6 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 User Mode Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 I/O and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 MC68HC05P18A MOTOROLA Table of Contents Technical Data 5 N O N - D I S C L O S U R E 1.5 Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.5.1 Power Supply (VDD and VSS) . . . . . . . . . . . . . . . . . . . . . . . .20 1.5.2 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . .20 1.5.2.1 Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5.2.2 Ceramic Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.5.2.3 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.5.3 Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.5.4 Port A (PA0–PA7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.5.5 Port B (PB5/SDO, PB6/SDI, and PB7/SCK) . . . . . . . . . . . .23 1.5.6 Port C (PC0–PC2, PC3/AD3, PC4/AD2, PC5/AD1, PC6/AD0, and PC7/VREFH) . . . . . . . . . . . . . . . . . . . . . . .23 1.5.7 Port D (PD5/CKOUT and PD7/TCAP) . . . . . . . . . . . . . . . . .23 1.5.8 Timer Output Compare (TCMP) . . . . . . . . . . . . . . . . . . . . . .23 1.5.9 Maskable Interrupt Request (IRQ) . . . . . . . . . . . . . . . . . . . .24 1.5.10 CPU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 A G R E E M E N T R E Q U I R E D Table of Contents R E Q U I R E D Section 3. Central Processor Unit (CPU) 3.1 3.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 A G R E E M E N T 3.3 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 3.3.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 3.3.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 3.3.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 3.3.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 3.3.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.4 Arithmetic/Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Section 4. Interrupts 4.1 4.2 4.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 CPU Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 N O N - D I S C L O S U R E 4.4 Interrupt Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 4.4.1 Reset Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . .42 4.4.2 Software Interrupt (SWI). . . . . . . . . . . . . . . . . . . . . . . . . . . .42 4.4.3 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 4.4.3.1 External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . .43 4.4.3.2 Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . .43 4.4.3.3 Output Compare Interrupt . . . . . . . . . . . . . . . . . . . . . . . .44 4.4.3.4 Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . .44 Section 5. Resets 5.1 5.2 5.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 5.4 Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 5.4.1 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 5.4.2 Computer Operating Properly (COP) Reset . . . . . . . . . . . . .47 5.4.3 Low-Voltage Reset (LVR). . . . . . . . . . . . . . . . . . . . . . . . . . .48 Technical Data 6 Table of Contents MC68HC05P18A MOTOROLA Table of Contents Section 6. Operating Modes 6.1 6.2 6.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 6.5 COP Watchdog Timer Considerations . . . . . . . . . . . . . . . . . . .54 Section 7. Input/Output (I/O) Ports 7.1 7.2 7.3 7.4 7.5 7.6 7.7 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 I/O Port Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Section 8. 16-Bit Timer 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Timer Operation during Wait Mode and Halt Mode . . . . . . . . .74 Timer Operating during Stop Mode . . . .