Voltage Detector

◆CMOS ◆Highly Accurate : +2% ◆Low Power Consumption : 0.9µA (TYP.) (VDF=1.9V, VIN = 2.0V) ◆Built-In Delay Circuit, Delay Pin Available ■APPLICATIONS ●Microprocessor reset circuitry ●Charge voltage monitors ●Memory battery back-up switch circuits ●Power failure detection circuits ■GENERAL DESCRIPTION The XC6109 series is highly precise, low power consumption voltage detector, manufactured using CMOS and laser trimming technologies. With the built-in delay circuit, connecting the delay capacitance pin to the capacitor enables the IC to provide an arbitrary release delay time. Using an ultra small package (SSOT-24), the series is suited for high density mounting. are available. ■FEATURES Highly Accurate : +2% (Setting Voltage Accuracy>1.5V) : +30mV (Setting Voltage Accuracy<1.5V) Low Power Consumption Detect Voltage Range : 0.9 µA (TYP., VDF=1.9V, VIN= 2.0V) : 0.8V ~ 5.0V in 100mV increments Operating Voltage Range : 0.7V ~ 6.0V Both CMOS and N-channel open drain output configurations www.DataSheet4U.com Detect Voltage Temperature Characteristics : ±100ppm/ OC (TYP.) Output Configuration : CMOS or N-channel open drain Operating Temperature Range : -40 OC ~ +85 OC Ultra Small Package : SSOT-24 ■TYPICAL APPLICATION CIRCUIT ■TYPICAL PERFORMANCE CHARACTERISTICS ●Release Delay Time vs. Delay Capacitance XC6109xxxA N VIN(MIN.)=0.7V,VIN(MAX.)=6.0V VIN VIN Cd VSS Cd VOUT R=100kΩ (No resistor needed for CMOS output products) Release Delay Time: TDR (ms) 10000 1000 100 10 1 0.1 0.0001 Tr=5µs, Ta=25℃ 0.001 0.01 0.1 Delay Capacitance: Cd (µF) 1 XC6109 ETR0206_003 1/13 XC6109 Series ■PIN CONFIGURATION ■PIN ASSIGNMENT PIN NUMBER 1 2 3 4 PIN NAME VIN VSS Cd VOUT FUNCTION Input Ground Delay Capacitance Output (Detect ”L”) ■PRODUCT CLASSIFICATION ●Ordering Information XC6109 ①②③④⑤⑥ DESIGNATOR ① ② ③ ④ ⑤ ⑥ DESCRIPTION Output Configuration Detect Voltage Output Delay & Hysteresis Package Device Orientation SYMBOL C N 08 ~ 50 A N R L : CMOS output : N-ch open drain output : e.g. 18→1.8V : Built-in delay pin & hysteresis 5% (TYP.) : SSOT-24 : Embossed tape, standard feed : Embossed tape, reverse feed DESCRIPTION 2/13 XC6109 Series ■PACKAGING INFORMATION ●SSOT-24 ■MARKING RULE ●SSOT-24 4 3 ① Represents output configuration and integer number of detect voltage CMOS output (XC6109C Series) N-ch Open Drain output (XC6109N Series) MARK VOLTAGE (V) A 0.x B 1.x C 2.x D 3.x E 4.x F 5.x PRODUCT SERIES XC6109C0xxNx XC6109C1xxNx XC6109C2xxNx XC6109C3xxNx XC6109C4xxNx XC6109C5xxNx MARK VOLTAGE (V) K 0.x L 1.x M 2.x N 3.x P 4.x R 5.x PRODUCT SERIES XC6109N0xxNx XC6109N1xxNx XC6109N2xxNx XC6109N3xxNx XC6109N4xxNx XC6109N5xxNx ① ② ④ 1 2 SSOT-24 (TOP VIEW) ②Represents decimal number of detect voltage MARK N P R S T U V X Y Z VOLTAGE (V) x.0 x.1 x.2 x.3 x.4 x.5 x.6 x.7 x.8 x.9 PRODUCT SERIES XC6109xx0xNx XC6109xx1xNx XC6109xx2xNx XC6109xx3xNx XC6109xx4xNx XC6109xx5xNx XC6109xx6xNx XC6109xx7xNx XC6109xx8xNx XC6109xx9xNx ④Represents production lot number 0 to 9, A to Z or inverted characters of 0 to 9, A to Z repeated/ (G, I, J, O, Q, W excepted) 3/13 XC6109 Series ■BLOCK DIAGRAMS (1) XC6109C (CMOS Output) (2) XC6109N (N-ch Open Drain Output) 4/13 XC6109 Series ■ABSOLUTE MAXIMUM RATINGS PARAMETER Input Voltage Output Current Output Voltage XC6109C (*1) XC6109N (*2) SYMBOL VIN IOUT VOUT VCD ICD Pd Ta Tstg RATINGS VSS - 0.3 ~ 7.0 10 VSS - 0.3 ~ VIN + 0.3 VSS - 0.3 ~ 7.0 VSS-0.3 ~ VIN + 0.3 5.0 150 - 40 ~ + 85 - 40 ~ + 125 Ta = 25OC UNITS V mA V V mA mW O O Delay Pin Voltage Delay Pin Current Power Dissipation SSOT-24 Operating Temperature Range Storage Temperature Range NOTE: *1: CMOS output *2: N-ch open drain output C C ■ELECTRICAL CHARACTERISTICS Ta = 25OC PARAMETER Operating Voltage Detect Voltage Hysteresis Range 1 Supply Current 1 SYMBOL VIN VDF VHYS1 ISS1 CONDITIONS VDF(T)=0.8~5.0V (*1) VDF(T)=0.8~5.0V VIN=1.0~6.0V VDF(T)=0.8~1.9V VIN=VDF x 0.9 VDF(T)=2.0~3.9V VDF(T)=4.0~5.0V VDF(T)=0.8~1.9V VIN=VDF x 1.1 VDF(T)=2.0~3.9V VDF(T)=4.0~5.0V VIN=VDFx0.9 VDS=0.5V (N-ch) VIN=VDFx1.1 VDS=0.5V (P-ch) -40 OC VDF), the output voltage (VOUT) keeps the “High” level (=VIN). ② When the input pin voltage keeps dropping and becomes equal to the detect voltage (VIN = VDF), an N-ch transistor for the delay capacitance discharge is turned ON, and starts to discharge the delay capacitance. For the internal circuit, which uses the delay capacitance pin as power input, the reference voltage operates as a comparator of VIN, and the output voltage changes into the “Low” level (≦VIN×0.1). The detect delay time (TDF) is defined as time which ranges from VIN =VDF to the VOUT of “Low” level (especially, when the Cd pin is not connected: TDF0). ③ While the input pin voltage keeps below the detect voltage, and 0.7V or more, the delay capacitance is discharged to the ground voltage (=VSS) level. Then, the output voltage (VOUT) maintains the “Low” level. ④ While the input pin voltage drops to 0.7V or less and it increases again to 0.7V or more, the output voltage may not be able to maintain the “Low” level. Such an operation is called “Unspecified Operation”, and voltage which occurs at the output pin voltage is defined as unstable operating voltage (VUNS). ⑤ While the input pin voltage increases more than 0.7V and it reaches to the release voltage level (VIN＜VDF +VHYS), the output voltage (VOUT) maintains the “Low” level. ⑥ When the input pin voltage continues to increase more than 0.7V up to the release voltage level (= VDF + VHYS), the N-ch transistor for the delay capacitance discharge will be turned OFF, and the delay capacitance will be started discharging via a delay resistor (Rdelay). The internal circuit, which uses the delay capacitance pin as power input, will operate as a hysteresis comparator (Rise Logic Threshold: VTLH=VTCD, Fall Logic Threshold: VTHL=VSS) while the input pin voltage keeps higher than the detect voltage (VIN > VDF). ⑦ While the input pin voltage becomes equal to the release voltage or higher and keeps the detect voltage or highe