210MHz Triple Video Digitizer

IGNS D ES I B L E W R NE PA T D FO 0% COM DE EN 10 I VE ATData Sheet IS A OM M REC 001-210 ALTERN N O T S L9 8 D I O VE T HE I M PR ® X98021 March 8, 2006 FN8219.3 210MHz Triple Video Digitizer with Digital PLL The X98021 3-channel, 8-bit Analog Front End (AFE) contains all the components necessary to digitize analog RGB or YUV graphics signals from personal computers, workstations and video set-top boxes. The fully differential analog design provides high PSRR and dynamic performance to meet the stringent requirements of the graphics display industry. The AFE’s 210MSPS conversion rate supports resolutions up to UXGA at 75Hz refresh rate, while the front end's high input bandwidth ensures sharp images at the highest resolutions. To minimize noise, the X98021's analog section features 2 sets of pseudo-differential RGB inputs with programmable input bandwidth, as well as internal DC restore clamping (including mid-scale clamping for YUV signals). This is followed by the programmable gain/offset stage and the three 210MSPS Analog-to-Digital Converters (ADCs). Automatic Black Level Compensation (ABLC™) eliminates part-to-part offset variation, ensuring perfect black level performance in every application. The X98021's digital PLL generates a pixel clock from the www.DataSheet4U.com analog source's HSYNC or SOG (Sync-On-Green) signals. Pixel clock output frequencies range from 10MHz to 210MHz with sampling clock jitter of 250ps peak to peak. Features • 210MSPS maximum conversion rate • Low PLL clock jitter (250ps p-p @ 210MSPS) • 64 interpixel sampling positions • 0.35Vp-p to 1.4Vp-p video input range • Programmable bandwidth (100MHz to 780MHz) • 2 channel input multiplexer • RGB and YUV 4:2:2 output formats • 5 embedded voltage regulators allow operation from single 3.3V supply and enhance performance, isolation • Completely independent 8 bit gain/10 bit offset control • CSYNC and SOG support • Trilevel sync detection • 1.1W typical PD @ 210MSPS • Pb-free plus anneal available (RoHS compliant) Applications • LCD Monitors and Projectors • Digital TVs • Plasma Display Panels • RGB Graphics Processing • Scan Converters Simplified Block Diagram RGB/YPbPrIN 1 RGB/YPbPrIN 2 3 3 Voltage Clamp PGA + Offset DAC ABLC™ 8 or 16 8 bit ADC x3 RGB/YUVOUT HSYNCOUT VSYNCOUT SOGIN1/2 HSYNCIN1/2 VSYNCIN1/2 Sync Processing Digital PLL HSOUT PIXELCLKOUT AFE Configuration and Control 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X98021 Ordering Information PART NUMBER X98021L128-3.3 X98021L128-3.3-Z (See Note) PART MARKING X98021L-3.3 X98021L-3.3Z MAXIMUM PIXEL RATE 210MHz 210MHz TEMP RANGE (°C) 0 to 70 0 to 70 PACKAGE 128 MQFP 128 MQFP (Pb-free) NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Block Diagram VCLAMP Offset DAC 10 ABLC™ RIN1 VIN+ VIN- 8 RIN2 PGA VCLAMP + 8 bit ADC 8 8 RP[7:0] RS[7:0] Offset DAC 10 ABLC™ Output Data Formatter GIN1 RGBGND1 GIN2 RGBGND2 VIN+ VIN- 8 8 PGA VCLAMP + 8 bit ADC 8 GP[7:0] GS[7:0] Offset DAC 10 ABLC™ BIN1 VIN+ VIN- 8 8 BIN2 PGA + 8 bit ADC 8 BP[7:0] BS[7:0] DATACLK SOGIN1 SOGIN2 HSYNCIN1 HSYNCIN2 VSYNCIN1 VSYNCIN2 HSYNCOUT CLOCKINV XTALIN XTALOUT SCL SDA SADDR VSYNCOUT DATACLK Sync Processing AFE Configuration and Control HSOUT VSOUT Digital PLL Serial Interface XTALCLKOUT 2 FN8219.3 March 8, 2006 X98021 Absolute Maximum Ratings Voltage on VA, VD, or VX (referenced to GNDA=GNDD=GNDX) . . . . . . . . . . . . . . . . . . . 4.0V Voltage on any analog input pin (referenced to GNDA) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VA Voltage on any digital input pin (referenced to GNDD) . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V Current into any output pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA Operating Temperature range . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Recommended Operating Conditions Temperature (Commercial) . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . VA = VD = VX = 3.3V CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Electrical Specifications SYMBOL T Specifications apply for VA = VD = VX = 3.3V, pixel rate = 210MHz, fXTAL = 25MHz, TA = 25°C, unless otherwise noted COMMENT MIN TYP MAX UNIT PARAMETER FULL CHANNEL CHARACTERISTICS ADC Resolution Missing Codes Conversion Rate DNL INL Differential Non-Linearity Integral Non-Linearity Gain Adjustment Range Gain Adjustment Resolution Gain Matching Between Channels Percent of full scale Guaranteed monotonic Per Channel 10 ±0.6 ±1.25 ±6 8 ±1 ±0.125 ±127 5 ±0.5 8 None 210 +1.0 -0.9 ±3.25 MHz LSB LSB dB Bits % LSB LSB ns Bits Full Channel Offset Error, ABLC™ enabled ADC LSBs, over time and temperature Offset Adjustment Range, ABLC™ enabled or disabled Overvoltage Recovery Time ADC LSBs (see ABLC™ applications information section) For 150% overrange, maximum bandwidth setting ANALOG VIDEO INPUT CHARACTERISTICS (RIN1, GIN1, BIN1, RIN2, GIN2, BIN2) Input Range Input Bias Current Input Capacitance Full Power Bandwidth INPUT CHARACTERISTICS (SOGIN1, SOGIN2) VIH/VIL Input Threshold Voltage Hysteresis Input capacitance INPUT CHARACTERISTICS (HSYNCIN1, HSYNCIN2) VIH/VIL Input Threshold Voltage Hysteresis RIN Input impedance Programmable - See Register Listing for Details Centered around threshold voltage 0.4 to 3.2 240 1.2 V mV kΩ Programmable - See Register Listing for Details Centered around threshold voltage 0 to -0.3 40 5 V mV pF Programmable DC restore clamp off 0.35 0.7 ±0.01 5 780 1.4 ±1 VP-P µA pF MHz 3 FN8219.3 March 8, 2006 X98021 Electrical Specifications SYMBOL Specifications apply for VA = VD = VX = 3.3V, pixel rate = 210MHz, fXTAL = 25MHz, TA = 25°C, unless otherwise noted (Continued) COMMENT MIN TYP 5 MAX UNIT pF PARAMETER Input capacitance DIGITAL INPUT CHARACTERISTICS (SDA, SADDR, CLOCKINVIN, RESET) VIH VIL I Input HIGH Voltage Input LOW Voltage Input leakage current Input capacitance SCHMITT DIGITAL INPUT CHARACTERISTICS (SCL, VSYNCIN1, VSYNCIN2) VT + VTI Low to High Threshold Voltage High to Low Threshold Voltage Input leakage current Input capacitance DIGITAL OUTPUT CHARACTERISTICS (DATACLK, DATACLK) VOH VOL Output HIGH Voltage, IO = 16mA Output LOW Voltage, IO = -16mA 2.4 0.4 V V ±10 5 1.45 0.95 V V nA pF RESET has a 70kΩ pullup to VD ±10 5 2.0 0.8 V V nA pF DIGITAL OUTPUT CHARACTERISTICS (RP, GP, BP, RS, GS, BS, HSOUT, VSOUT, HSYNCOUT, VSYNCOUT) VOH VOL RTRI Output HIGH Voltage, IO = 8mA Output LOW Voltage, IO = -8mA Pulldown to GNDD when three-state RP, GP, BP, RS, GS, BS only 58 2.4 0.4 V V kΩ DIGITAL OUTPUT CHARACTERISTICS (SDA, XTALCLKOUT) VOH VOL Output HIGH Voltage, IO = 4mA Output LOW Voltage, IO = -4mA XTALCLKOUT only; SDA is open-drain 2.4 0.4 V V POWER SUPPLY REQUIREMENTS VA VD VX IA ID IX PD Analog Supply Voltage Digital Supply Voltage Crystal Oscillator Supply Voltage Analog Supply Current Digital Supply Current Crystal Oscillator Supply Current Total Power Dissipation Operating (average) Power-down Mode ΘJA Thermal Resistance, Junction to Ambient Operating Operating (grayscale) 3 3 3 3.3 3.3 3.3 185 145 0.7 1.1 50 30 3.6 3.6 3.6 200 160 2 1.3 80 V V V mA mA mA W mW °C/W AC TIMING CHARACTERISTICS PLL Jitter Sampling Phase Steps Sampling Phase Tempco Sampling Phase Differential Nonlinearity HSYNC Frequency Range fXTAL Crystal Frequency Range Degrees out of 360° 10 23 25 5.6° per step 64 ±1 ±3 150 27 ps/°C ° kHz MHz 250 450 ps p-p 4 FN8219.3 March 8, 2006 X98021 Electrical Specifications SYMBOL tSETUP tHOLD Specifications apply for VA = VD = VX = 3.3V, pixel rate = 210MHz, fXTAL = 25MHz, TA = 25°C, unless otherwise noted (Continued) COMMENT MIN 1.3 2.0 TYP MAX UNIT ns ns PARAMETER DATA valid before rising edge of DATACLK 15pF DATACLK load, 15pF DATA load (Note 1) DATA valid after rising edge of DATACLK 15pF DATACLK load, 15pF DATA load (Note 1) AC TIMING CHARACTERISTICS (2 WIRE INTERFACE) fSCL SCL Clock Frequency Maximum width of a glitch on SCL that will be suppressed tAA tBUF tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tDH NOTES: 1. Setup and hold times are at a 140MHz DATACLK rate. SCL LOW to SDA Data Out Valid Time the bus must be free before a new transmission can start Clock LOW Time Clock HIGH Time Start Condition Setup Time Start Condition Hold Time Data In Setup Time Data In Hold Time Stop Condition Setup Time Data Output Hold Time 4 XTAL periods min 2 XTAL periods min 5 XTAL periods plus SDA’s RC time constant 1.3 1.3 0.6 0.6 0.6 100 0 0.6 160 0 80 See comment 400 kHz ns µs µs µs µs µs µs ns ns µs ns tF SCL tSU:ST SDA IN tHD:STA tSU:DAT tHIGH tLOW tR tHD:DAT tSU:STO tAA SDA OUT tDH tBUF FIGURE 1. 2 WIRE IN