®
X95820
Dual Digital Controlled Potentiometers (XDCP™)
Data Sheet July 18, 2006 FN8212.2
Low Noise/Low Power/I2C® Bus/256 Taps
The X95820 integrates two digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated circuit. The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the I2C bus interface. Each potentiometer has an associated volatile Wiper Register (WR) and a non-volatile Initial Value Register (IVR), that can be directly written to and read by the user. The contents of the WR controls the position of the wiper. At power up the device recalls the contents of the two DCP’s IVR to the corresponding WRs. The DCPs can be used as three-terminal potentiometers or as two-terminal variable resistors in a wide variety of applications including control, parameter adjustments, and signal processing.
Features
• Two potentiometers in one package • 256 resistor taps-0.4% resolution • I2C serial interface - Three address pins, up to eight devices/bus • Wiper resistance: 70Ω typical @ 3.3V • Non-volatile storage of wiper position • Standby current < 5µA max • Power supply: 2.7V to 5.5V • 50kΩ, 10kΩ total resistance • High reliability - Endurance: 150,000 data changes per bit per register - Register data retention: 50 years @ T ≤ 75°C • 14 Ld TSSOP • Pb-free plus anneal available (RoHS compliant)
Ordering Information
PART NUMBER X95820WV14I-2.7* www.DataSheet4U.com PART MARKING X95820WV G RESISTANCE OPTION 10kΩ 10kΩ 50kΩ 50kΩ PACKAGE 14 Ld TSSOP 14 Ld TSSOP (Pb-free) 14 Ld TSSOP 14 Ld TSSOP (Pb-free)
Pinouts
X95820 (14 LD TSSOP) TOP VIEW
VCC WP RH0 RL0 RW0 A2 SCL 1 2 3 4 5 6 7 14 13 12 11 10 9 8 A1 A0 RH1 RL1 RW1 GND SDA
X95820WV14IZ-2.7* X95820WV Z G (Note) X95820UV14I-2.7* X95820UV G
X95820UV14IZ-2.7* X95820UV Z G (Note) *Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X95820 Block Diagram
VCC
I2C INTERFACE SDA SCL
POWER-UP, INTERFACE, CONTROL AND STATUS LOGIC
RH1 WR1 RW1 RL1
A2 A1 A0 NON-VOLATILE REGISTERS WR0 RH0 RW0 RL0
WP
GND
PiN Descriptions
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SYMBOL VCC WP RH0 RL0 RW0 A2 SCL SDA GND RW1 RL1 RH1 A0 A1 Power supply pin Hardware write protection pin. Active low. Prevents any “Write” operation of the I2C interface. “High” terminal of DCP0 “Low” terminal of DCP0 “Wiper” terminal of DCP0 Device address for the I2C interface I2C interface clock Serial data I/O for the I2C interface Ground “Wiper” terminal of DCP1 “Low” terminal of DCP1 “High” terminal of DCP1 Device address for the I2C interface Device address for the I2C interface DESCRIPTION
2
FN8212.2 July 18, 2006
X95820
Absolute Maximum Ratings
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Voltage at Any Digital Interface Pin with Respect to GND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V Voltage at Any DCP Pin with Respect to GND . . . . . . -0.3V to VCC Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . . 300°C IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
Recommended Operating Conditions
Temperature Range (Industrial) . . . . . . . . . . . . . . . . . . -40°C to 85°C VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Power Rating of Each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW Wiper Current of Each DCP. . . . . . . . . . . . . . . . . . . . . . . . . . ±3.0mA
CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Analog Specifications
SYMBOL RTOTAL
Over recommended operating conditions unless otherwise stated. TEST CONDITIONS W, U versions respectively -20 VCC = 3.3V @ 25°C Wiper current = VCC/RTOTAL 70 10/10/25 Voltage at pin from GND to VCC 0.1 1 MIN TYP (Note 1) 10, 50 +20 200 MAX UNIT kΩ % Ω pF µA
PARAMETER RH to RL Resistance RH to RL Resistance Tolerance
RW CH/CL/CW ILkgDCP
Wiper Resistance Potentiometer Capacitance (Note 15) Leakage on DCP Pins (Note 15)
VOLTAGE DIVIDER MODE (0V @ RLi; VCC @ RHi; measured at RWi, unloaded; i = 0 or 1) INL (Note 6) Integral Non-linearity Monotonic over all tap positions U option W option Full-scale Error U option W option DCP to DCP Matching Any two DCPs at same tap position, same voltage at all RH terminals, and same voltage at all RL terminals DCP Register set to 80 hex -1 -0.5 0 0 -7 -2 -2 1 0.5 -1 -1 1 0.5 7 2 0 0 2 LSB (Note 2) LSB (Note 2) LSB (Note 2) LSB (Note 2) LSB (Note 2) ppm/°C
DNL (Note 5) Differential Non-linearity ZSerror (Note 3) FSerror (Note 4) VMATCH (Note 7) Zero-scale Error
TCV (Note 8) Ratiometric Temperature Coefficient
±4
RESISTOR MODE (Measurements between RWi and RLi with RHi not connected, or between RWi and RHi with RLi not connected. i = 0 or 1) RINL (Note 12) RDNL (Note 11) Roffset (Note 10) Integral Non-linearity Differential Non-linearity Offset DCP Register set to 00 hex, U option DCP Register set to 00 hex, W option RMATCH (Note 13) TCR (Note 14) DCP to DCP Matching Resistance Temperature Coefficient Any two DCPs at the same tap position with the same terminal voltages. DCP register set between 20 hex and FF hex DCP register set between 20 hex and FF hex. Monotonic over all tap positions -1 -0.5 0 0 -2 ±45 1 0.5 1 0.5 7 2 2 MI (Note 9) MI (Note 9) MI (Note 9) MI (Note 9) MI (Note 9) ppm/°C
3
FN8212.2 July 18, 2006
X95820
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL ICC1 ICC2 ISB PARAMETER VCC Supply Current (Volatile write/read) VCC Supply Current (nonvolatile write) VCC Current (standby) TEST CONDITIONS fSCL = 400kHz;SDA = Open; (for I2C, Active, Read and Volatile Write States only) fSCL = 400kHz; SDA = Open; (for I2C, Active, Nonvolatile Write State only) VCC = +5.5V, I2C Interface in Standby State VCC ILkgDig = +3.6V, I2C Interface in Standby State -10 MIN TYP (Note 1) MAX 1 3 5 2 10 UNITS mA mA µA µA µA
Leakage Current, at Pins A0, Voltage at pin from GND to VCC A1, A2, SDA, SCL, and WP Pins DCP Wiper Response Time Power-on Recall Voltage VCC Ramp Rate Power-up Delay VCC above Vpor, to DCP Initial Value Register recall completed, and I2C Interface in standby state SCL falling edge of last bit of DCP Data Byte to wiper change Minimum VCC at which memory recall occurs
tDCP (Note 15) Vpor VccRamp tD (Note 15)
1 1.8 0.2 3 2.6
µs V V/ms ms
EEPROM SPECS EEPROM Endurance EEPROM Retention SERIAL INTERFACE SPECS VIL WP, A2, A1, A0, SDA, and SCL input buffer LOW voltage WP, A2, A1, A0, SDA, and SCL Input Buffer HIGH Voltage SDA and SCL input buffer hysterisis SDA Output Buffer LOW Voltage, Sinking 4mA WP, A2, A1, A0, SDA, and SCL Pin Capacitance SCL Frequency Pulse Width Suppression Any pulse narrower than the max spec is Time at SDA and SCL Inputs suppressed. SCL Falling Edge to SDA Output Data Valid Time the Bus Must be Free Before the Start of a New Transmission Clock LOW Time Clock HIGH Time START Condition Setup Time START Condition Hold Time SCL falling edge crossing 30% of VCC, until SDA exits the 30% to 70% of VCC window. SDA crossing 70% of VCC during a STOP condition, to SDA crossing 70% of VCC during the following START condition. Measured at the 30% of VCC crossing. Measured at the 70% of VCC crossing. SCL rising edge to SDA falling edge. Both crossing 70% of VCC. From SDA falling edge crossing 30% of VCC to SCL falling edge crossing 70% of VCC. 1300 -0.3 0.3*Vcc V Temperature ≤ 75°C 150,000 50 Cycles Years
VIH
0.7*Vcc
Vcc+0.3
V
Hysterisis (Note 15) VOL (Note 15) Cpin (Note 15) fSCL tIN (Note 15) tAA (Note 15) tBUF (Note 15) tLOW tHIGH tSU:STA tHD:STA
0.05* Vcc 0 0.4 10 400 50 900
V V pF kHz ns ns ns
1300 600 600 600
ns ns ns ns
4
FN8212.2 July 18, 2006
X95820
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL tSU:DAT tHD:DAT tSU:STO tHD:STO PARAMETER Input Data Setup Time Input Data Hold Time TEST CONDITIONS From SDA exiting the 30% to 70% of VCC window, to SCL rising edge crossing 30% of VCC From SCL rising edge crossing 70% of VCC to SDA entering the 30% to 70% of VCC window. MIN 100 0 600 600 0 20 + 0.1 * Cb 20 + 0.1 * Cb 10 1 250 250 400 TYP (Note 1) MAX UNITS ns ns ns ns ns ns ns pF kΩ
STOP Condition Setup Time From SCL rising edge crossing 70% of VCC, to SDA rising edge crossing 30% of VCC. STOP Condition Setup Time From SDA rising edge to SCL falling edge. Both crossing 70% of VCC. From SCL falling edge crossing 30% of VCC, until SDA enters the 30% to 70% of VCC window. From 30% to 70% of VCC From 70% to 30% of VCC Total on-chip and of
