Stereo CODEC

Part  Number WM8960
Manufacturer Wolfson Microelectronics
Semiconductor DataSheet

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w DESCRIPTION The WM8960 is a low power, high quality stereo codec designed for portable digital audio applications. WM8960 Stereo CODEC with 1W Stereo Class D Speaker Drivers and Headphone Drivers for Portable Audio Applications FEATURES • • • • • DAC SNR 98dB (‘A’ weighted), THD -84dB at 48kHz, 3.3V ADC SNR 94dB (‘A’ weighted), THD -82dB at 48kHz, 3.3V Pop and click suppression Stereo class D speaker drivers provide 1W per channel into 8Ω 3D Enhancement loads with a 5V supply. Low leakage, excellent PSRR and Stereo Class D Speaker Driver pop/click suppression mechanisms also allow direct battery • <0.1% THD with 1W per channel into 8Ω BTL speakers connection to the speaker supply. Flexible speaker boost • 70dB PSRR @217Hz settings allow speaker output power to be maximised while • 87% efficiency (1W output) minimising other analogue supply currents. • Flexible internal switching clock • On-chip Headphone Driver A highly flexible input configuration for up to three stereo • 40mW output power into 16Ω at 3.3V sources is integrated, with a complete microphone interface. • Capless mode support External component requirements are drastically reduced as no • THD -75dB at 20mW, SNR 90dB with 16Ω load separate microphone, speaker or headphone amplifiers are • Microphone Interface required. Advanced on-chip digital signal processing performs • Pseudo differential for high noise immunity automatic level control for the microphone or line input. • Integrated low noise MICBIAS • Programmable ALC / Limiter & Noise Gate Stereo 24-bit sigma-delta ADCs and DACs are used with low Low Power Consumption power over-sampling digital interpolation and decimation filters • • 10mW headphone playback (2.7V / 1.8V supplies) and a flexible digital audio interface. • 20mW record and playback (2.7V / 1.8V supplies) The master clock can be input directly or generated internally by • Low Supply Voltages an onboard PLL, supporting most commonly-used clocking • Analogue 2.7V to 3.6V (Speaker supply up to 5.5V) www.DataSheet4U.com schemes. • Digital core and I/O: 1.71V to 3.6V On-chip PLL provides flexible clocking scheme The WM8960 operates at analogue supply voltages down to • Sample rates: 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, 48 2.7V, although the digital supplies can operate at voltages down • 5x5x0.9mm QFN package to 1.71V to save power. The speaker supply can operate at up • to 5.5V, providing 1W per channel into 8Ω loads. Unused functions can be disabled using software control to save power. The WM8960 is supplied in a very small and thin 5x5mm QFN package, ideal for use in hand-held and portable systems. APPLICATIONS • • • Games consoles Portable media / DVD players Mobile multimedia WOLFSON MICROELECTRONICS plc To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/ Preliminary Technical Data, September 2006, Rev 2.0 Copyright 2006 Wolfson Microelectronics plc WM8960 Preliminary Technical Data TABLE OF CONTENTS DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................3 ORDERING INFORMATION ..................................................................................3 PIN DESCRIPTION ................................................................................................4 ABSOLUTE MAXIMUM RATINGS.........................................................................5 RECOMMENDED OPERATING CONDITIONS .....................................................5 ELECTRICAL CHARACTERISTICS ......................................................................6 OUTPUT PGA GAIN.............................................................................................10 TYPICAL POWER CONSUMPTION ....................................................................11 SIGNAL TIMING REQUIREMENTS .....................................................................12 SYSTEM CLOCK TIMING............................................................................................ 12 AUDIO INTERFACE TIMING – MASTER MODE ......................................................... 12 AUDIO INTERFACE TIMING – SLAVE MODE ............................................................ 13 CONTROL INTERFACE TIMING – 2-WIRE MODE ..................................................... 14 INTERNAL POWER ON RESET CIRCUIT ..........................................................15 DEVICE DESCRIPTION.......................................................................................17 INTRODUCTION.......................................................................................................... 17 INPUT SIGNAL PATH.................................................................................................. 18 ANALOGUE TO DIGITAL CONVERTER (ADC) .......................................................... 25 AUTOMATIC LEVEL CONTROL (ALC) ....................................................................... 27 OUTPUT SIGNAL PATH.............................................................................................. 30 ANALOGUE OUTPUTS ............................................................................................... 36 ENABLING THE OUTPUTS ......................................................................................... 40 HEADPHONE OUTPUT ............................................................................................... 40 CLASS D SPEAKER OUTPUTS .................................................................................. 41 VOLUME UPDATES .................................................................................................... 42 HEADPHONE JACK DETECT ..................................................................................... 44 THERMAL SHUTDOWN .............................................................................................. 45 GENERAL PURPOSE INPUT/OUTPUT ...................................................................... 46 DIGITAL AUDIO INTERFACE...................................................................................... 47 AUDIO INTERFACE CONTROL .................................................................................. 51 CLOCKING AND SAMPLE RATES .............................................................................. 55 CONTROL INTERFACE .............................................................................................. 62 POWER MANAGEMENT ............................................................................................. 62 REGISTER MAP...................................................................................................66 REGISTER BITS BY ADDRESS .................................................................................. 67 DIGITAL FILTER CHARACTERISTICS ...............................................................81 ADC FILTER RESPONSES ......................................................................................... 81 DAC FILTER RESPONSES ......................................................................................... 82 DE-EMPHASIS FILTER RESPONSES ........................................................................ 83 APPLICATIONS INFORMATION .........................................................................84 RECOMMENDED EXTERNAL COMPONENTS........................................................... 84 IMPORTANT NOTICE ..........................................................................................88 ADDRESS:................................................................................................................... 88 w PTD, September 2006, Rev 2.0 2 Preliminary Technical Data WM8960 PIN CONFIGURATION 32 31 30 29 28 27 26 25 24 SPKGND1 23 SPK_LN 22 SPK_RP MICBIAS LINPUT3/JD2 LINPUT2 LINPUT1 RINPUT1 RINPUT2 RINPUT3/JD3 DCVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TOP VIEW 21 SPKVDD2 20 SPKGND2 19 SPK_RN 18 SDIN 17 SCLK ORDERING INFORMATION ORDER CODE WM8960GEFL/V WM8960GEFL/RV Note: Reel quantity = 3500 TEMPERATURE RANGE -40°C to +85°C -40°C to +85°C PACKAGE 32-pin QFN (5x5x0.9mm) (Pb-free) 32-pin QFN (5x5x0.9mm) (Pb-free, Tape and reel) MOISTURE SENSITIVITY LEVEL MSL3 MSL3 PEAK SOLDERING TEMPERATURE 260°C 260°C w PTD, September 2006, Rev 2.0 3 WM8960 PIN DESCRIPTION PIN NO 1 2 NAME MICBIAS LINPUT3 / JD2 TYPE Analogue Output Analogue Input Microphone bias Preliminary Technical Data DESCRIPTION Left channel line input / Left channel positive differential MIC input / Jack detect input pin Left channel line input / Left channel positive differential MIC input Left channel single-ended MIC input / Left channel negative differential MIC input Right channel single-ended MIC input / Right channel negative differential MIC input Right channel line input / Right channel positive differential MIC input Right channel line input / Right channel positive differential MIC input / Jack detect input pin Digital core supply Digital ground (Return path for both DCVDD and DBVDD) Digital buffer (I/O) supply Master clock Audio interface bit clock Audio interface DAC left / right clock DAC digital audio data Audio interface ADC left / right clock / GPIO1 pin ADC digital audio data Control interface clock input Control interface data input / 2-wire acknowledge output Right speaker negative output Ground for speaker drivers 2 Supply for speaker drivers 2 Right speaker positive output Left speaker negative




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