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Part Number |
WD8250 |
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Manufacturer |
Western Digital |
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Semiconductor DataSheet |
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DataSheet View |
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,',
www.DataSheet4U.com
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TABLE2. SUMMARY OF WD8250 ACCESSIBLE REGISTERS ,)FA.
~~gl~'~r AddntU
.,Jl3,h
ODlAB 1
'v g:
1'"
2
I
Bit No,
I Receiver
Buffer Aegistér
(Reed Only)
'. I
,lnterH/tH Ideriti'i- , 1
Line
catioo;," ,Control., 'Regíster ' 'Registei, Word
"
~;~Jt~~~~~t < Ré~igté,lg:'A~~tér:':l',l=Ieg!~te;'}: I
,
!~i~
';* O I DataBitO' IDetaBltO.
1,
"O'~iV:" Length;, Select' Interrupt Bit O Pending : I ,; (WLSO)
jf~~ff4
ii:~i!~~~~;
"
DataBitl
Data Bit 1
,""
Enable Transmitter Holding Register Empty, Interrupt
(ETBEI) Enable Receiver line Status Interrupt (ELS!) MODEM Status Interrupt (EOSSI)
,
Interrupt ID Bit (O)
Word Length Select Bit I (WLS 1)
c'
2'
Data Bit 2
OataBl12,v,",
Interrupt ID
Bit (1)
,
N'Jmber of Stop i Bits (STB)
Parity Out I
Trailing
Edge fb,ng
I
Error,~
(PE)
Indica,tor, (TERI) ,
.Enable
3
Data BII 3
Parity O
Enable (PEN)
I
Data Blt;3
B!
it4
b
I
4
Data 81!4
o
O
Even Parity Select (EPS)
I
LODP
5 Data Bit S
Data 81t 5
Transmitter
Data
O
o
Stlck Parity
I
O
>
HoldIng
Register E~pty (THRE)
Set Ready (OSR) .
I
Bit 5
'.
6
Data Bit 6
Data Bit 6
o
o
Set Break
O
Trans. mitter Shltt Register Empty (TSRE)
Ring Indlcator (RI)
Bit 6
'" ','
7
Data 81t 7
Data Bit 7 ::.
o
o
DIVIsor Latch Access Bit (DLAB) or
/
c!
o
o
'8,t O IS the least Significant
bit It IS the first bit senally transmitted
~6 bi~
~
'
.".
_If':;;' llL O'::ot..'.'
jf~;if~f~j"~1~fil
.
~,
. .
Receiver ;.);,;. Data Available
. '
.'~~~JW1i~!f~f;?"],'~:
. Jf;!e~cI.ingJhe.IIF:1,;,~.:,
O
, . ,','
R~gls"teL(it~4rC:~""J
,,-
;:~~fr~~~~I1~~~Y~~~;;~" .,1 Transmltter;Holding;.:-;
,
'ij~9Is}~(~1~;~h~~q§{i-?~;;~:-'.
,.,",..
Clearto
O
. :0-;.
Se"d
OrS;d-iB:~~:~tf~x'~~~~:~'f~i:J;",
Ore ~R~adlng:!~:tz).1~';Ü!r;;:.~~'~
.-Data Set Ready
O
Ring'lndicator or' :MODEM~S.af~s~~/~.:: :~;)~:
.~~~e~~~e~~~~
,--'.
.,"". ~~~'st~r.:::X~:~~6~'~;',.:~,~
:
gic 1~~n-e~e~ number of bits is transmitted or
iecked,
GeneratÖÍ'K-3:t
.
MHz:'
However:~:whe-r.
-.usrng"".'
,
t 5: This bit is the Stick Parity bit. When bit 3 is a 9'c 1 and bitS is a 109ic 1, the Parity bit is transmitd and then detected by the receiver in the opposite Jle indicated by bit 4, t 6: This bit is the Set Break Control bit. When bit 6 a 10gic 1, th~ serial output (SO UT) is forced 10 the SLE 3. BAUD RATES USING 1.8432 MHz CRYSTAl.
Desired Baud Rate 5J 75 110 13 5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38<100 Divisor Used 10 Generale 16x Clock 2304 1536 1047 657 768 384 192 96 64 58 48 32 24 16 12 6 3 Percent Error Dilference 8etween Desired and Actual -
, dlvl.sorsof 6,a~d below,'the maXimU'mfrequeri~y, Is equal to 1/2 the divisor InMHz. For example, if the divisor is 1, then the maximum frequenoy is 1/2 MHz. In no case should the data rate be greater than 56K Baud, Line Status Register This 8-bit register provides status information to the CPU concerning the data transfer. The contenls of TABlE 4. BAUDRATES USING 3.072 MHzCRYSTAl.
"
.. .
Desired Baud Rate 50
Divisor Used to Generale 16x Clock 3840
Percent
Error
DilltenCe andBetween Des ed Aclual
-
0.026 0.058
75
110 1345 150
2560
1745 1428 1280
-
-
0.026 0.034
-
0.69 -
-
300 600 1200 1800 2000 2400 3600 4800
7200 9600 19200 38400 56000
drvlded by 10.
-.
640 320 160 107 96 80 53 40
27 20 1(}. 5 3
'
0628
-
-
1.23 -
56000
2
286
'4 285
'Eo 18432 MHllS inc sta dard'OO80 trequcr1cy
-- --
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201
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