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Winbond
Winbond

W83977EF-AW Datasheet

WINBOND I/O


W83977EF-AW Datasheet Preview


W83977EF
WINBOND I/O
Page 1

W83977EF Data Sheet Revision History
Pages
1 n.a.
Dates Version
06/01/98 0.40
Version
on Web
Main Contents
First published.
For Beta Site customers only
2
4,7,49,50,53,55,
90,91
06/16/98
3 n.a.
12/30/03
0.41
0.5
Data correction
Remove W83977CTF Part
4
5 P86~P110
03/07/03
04/25/03
1.0
1.1
Update the new version on web
Add Chapter 10 Configuration Register
6
7
8
9
10
Please note that all data and specifications are subject to change without notice. All
the trade marks of products and companies mentioned in this data sheet belong to
their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or
systems where malfunction of these products can reasonably be expected to result in
personal injury. Winbond customers using or selling these products for use in such
applications do so at their own risk and agree to fully indemnify Winbond for any
damages resulting from such improper use or sales.
Page 2

W83977EF
TABLE OF CONTENTS
GENERAL DESCRIPTION ..................................................................................................................... 1
FEATURES ............................................................................................................................................. 2
PIN CONFIGURATION ........................................................................................................................... 5
1.0 PIN DESCRIPTION.......................................................................................................................... 6
1.1 HOST INTERFACE ............................................................................................................................. 6
1.2 GENERAL PURPOSE I/O PORT .......................................................................................................... 8
1.3 SERIAL PORT INTERFACE.................................................................................................................. 9
1.4 INFRARED INTERFACE..................................................................................................................... 10
1.5 MULTI-MODE PARALLEL PORT ........................................................................................................ 11
1.6 FDC INTERFACE ............................................................................................................................ 16
1.7 KBC INTERFACE ............................................................................................................................ 18
1.8 POWER PINS .............................................................................................................................. 18
1.9 ACPI INTERFACE ........................................................................................................................... 18
2.0 FDC FUNCTIONAL DESCRIPTION............................................................................................... 19
2.1 W83977EF FDC .......................................................................................................................... 19
2.1.1 AT interface ........................................................................................................................... 19
2.1.2 FIFO (Data) ........................................................................................................................... 19
2.1.3 Data Separator...................................................................................................................... 20
2.1.4 Write Precompensation......................................................................................................... 20
2.1.5 Perpendicular Recording Mode ............................................................................................ 21
2.1.5 Perpendicular Recording Mode ............................................................................................ 21
2.1.6 FDC Core .............................................................................................................................. 21
2.1.7 FDC Commands ................................................................................................................... 21
2.2 REGISTER DESCRIPTIONS............................................................................................................... 33
2.2.1 Status Register A (SA Register) (Read base address + 0) .................................................. 33
2.2.2 Status Register B (SB Register) (Read base address + 1) .................................................. 35
2.2.3 Digital Output Register (DO Register) (Write base address + 2).......................................... 37
2.2.4 Tape Drive Register (TD Register) (Read base address + 3) .............................................. 37
2.2.5 Main Status Register (MS Register) (Read base address + 4) ............................................ 38
2.2.6 Data Rate Register (DR Register) (Write base address + 4) ............................................... 38
2.2.7 FIFO Register (R/W base address + 5) ................................................................................ 40
2.2.8 Digital Input Register (DI Register) (Read base address + 7) .............................................. 42
2.2.9 Configuration Control Register (CC Register) (Write base address + 7) ............................. 43
3.0 UART PORT.................................................................................................................................... 45
3.1 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART A, UART B) .................................... 45
3.2 REGISTER ADDRESS ...................................................................................................................... 45
3.2.1 UART Control Register (UCR) (Read/Write) ........................................................................ 45
3.2.2 UART Status Register (USR) (Read/Write) .......................................................................... 48
3.2.3 Handshake Control Register (HCR) (Read/Write)................................................................ 48
Publication Release Date: April 2003
-II - Revision 1.1
Page 3

W83977EF
3.2.4 Handshake Status Register (HSR) (Read/Write) ................................................................. 49
3.2.5 UART FIFO Control Register (UFR) (Write only).................................................................. 50
3.2.6 Interrupt Status Register (ISR) (Read only).......................................................................... 51
3.2.7 Interrupt Control Register (ICR) (Read/Write) ...................................................................... 52
3.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write) .................................................... 52
3.2.9 User-defined Register (UDR) (Read/Write) .......................................................................... 52
4.0 INFRARED (IR) PORTS ................................................................................................................. 54
4.1 IR PORT ...................................................................................................................................... 54
5.0 PARALLEL PORT ......................................................................................................................... 55
5.1 PRINTER INTERFACE LOGIC ............................................................................................................ 55
5.2 ENHANCED PARALLEL PORT (EPP)................................................................................................. 56
5.2.1 Data Swapper ................................................................................................................. 56
5.2.2 Printer Status Buffer ........................................................................................................ 57
5.2.3 Printer Control Latch and Printer Control Swapper ........................................................ 58
5.2.4 EPP Address Port............................................................................................................ 58
5.2.5 EPP Data Port 0-3 ........................................................................................................... 59
5.2.6 Bit Map of Parallel Port and EPP Registers .................................................................... 59
5.2.7 EPP Pin Descriptions...................................................................................................... 60
5.2.8 EPP Operation................................................................................................................. 60
5.3 EXTENDED CAPABILITIES PARALLEL (ECP) PORT ........................................................................... 61
5.3.1 ECP Register and Mode Definitions ................................................................................ 61
5.3.2 Data and ecpAFifo Port ................................................................................................... 62
5.3.3 Device Status Register (DSR) ........................................................................................ 62
5.3.4 Device Control Register (DCR) ....................................................................................... 63
5.3.5 CFIFO (Parallel Port Data FIFO) Mode = 010................................................................. 64
5.3.6 ECPDFIFO (ECP Data FIFO) Mode = 011...................................................................... 64
5.3.7 TFIFO (Test FIFO Mode) Mode = 110 ............................................................................ 64
5.3.8 CNFGA (Configuration Register A) Mode = 111 ............................................................. 64
5.3.9 CNFGB (Configuration Register B) Mode = 111 ............................................................. 64
5.3.10 ECR (Extended Control Register) Mode = all ................................................................. 65
5.3.11 Bit Map of ECP Port Registers ........................................................................................ 66
5.3.12 ECP Pin Descriptions ...................................................................................................... 67
5.3.13 ECP Operation................................................................................................................. 68
5.3.14 FIFO Operation................................................................................................................ 68
5.3.15 DMA Transfers................................................................................................................. 69
5.3.16 Programmed I/O (NON-DMA) Mode ............................................................................... 69
5.4 EXTENSION FDD MODE (EXTFDD) .......................................................................................... 69
5.5 EXTENSION 2FDD MODE (EXT2FDD) ...................................................................................... 69
6. KEYBOARD CONTROLLER..................................................................................................... 70
6.1 OUTPUT BUFFER........................................................................................................................... 70
6.2 INPUT BUFFER .............................................................................................................................. 70
6.3 STATUS REGISTER ........................................................................................................................ 71
6.4 COMMANDS............................................................................................................................... 72
6.5 HARDWARE GATEA20/KEYBOARD RESET CONTROL LOGIC........................................................... 73
6.5.1 KB Control Register (Logic Device 5, CR-F0) ................................................................. 74
6.5.2 Port 92 Control Register (Default Value = 0x24)............................................................. 74
6.6 ONNOW / SECURITY KEYBOARD AND MOUSE WAKE-UP.............................................................. 75
Publication Release Date: April 2003
-III - Revision 1.1
Page 4
Part Number W83977EF-AW
Manufactur Winbond
Description WINBOND I/O
Total Page 30 Pages
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