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W79E549/W79L549 Data Sheet 8-BIT MICROCONTROLLER
Table of Contents1. 2. 3. 4. 5. 6. 7. 8. GENERAL DESCRIPTION ......................................................................................................... 3 FEATURES ................................................................................................................................. 3 PIN CONFIGURATIONS ............................................................................................................ 4 PIN DESCRIPTION..................................................................................................................... 5 BLOCK DIAGRAM ...................................................................................................................... 7 FUNCTIONAL DESCRIPTION ................................................................................................... 8 MEMORY ORGANIZATION ..................................................................................................... 10 INSTRUCTION.......................................................................................................................... 29 8.1 9. 10. 11. Instruction Timing ......................................................................................................... 29
8.1.1 External Data Memory Access Timing............................................................................32
POWER MANAGEMENT.......................................................................................................... 35 INTERRUPTS ........................................................................................................................... 38 PROGRAMMABLE TIMERS/COUNTERS ............................................................................... 40 11.1 11.2 11.3 11.4 Timer/Counters 0 & 1.................................................................................................... 40 Timer/Counter 2............................................................................................................ 43 Pulse Width Modulated Outputs (PWM)....................................................................... 47 Watchdog Timer ........................................................................................................... 50 Framing Error Detection ............................................................................................... 59 Multiprocessor Communications .................................................................................. 59
12.
SERIAL PORT .......................................................................................................................... 54 12.1 12.2
13. 14. 15.
TIMED ACCESS PROTECTION .............................................................................................. 61 H/W REBOOT MODE (BOOT FROM 4K BYTES OF LDFLASH) ............................................ 63 IN-SYSTEM PROGRAMMING ................................................................................................. 64 15.1 15.2 The Loader Program Locates at LDFlash Memory ...................................................... 64 The Loader Program Locates at APFlash Memory ...................................................... 64
16. 17. 18.
H/W WRITER MODE ................................................................................................................ 65 SECURITY BITS ....................................................................................................................... 66 ELECTRICAL CHARACTERISTICS......................................................................................... 67 18.1 18.2 18.3 Absolute Maximum Ratings .......................................................................................... 67 DC Characteristics........................................................................................................ 67 A.C. Characteristics ...................................................................................................... 69
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Publication Release Date: December 11, 2005 Revision A1
W79E549/W79L549
18.3.1 18.3.2 18.3.3 18.3.4 18.3.5 A.C. Specification .........................................................................................................69 MOVX Characteristics Using Strech Memory Cycle .....................................................70 Program Memory Read Cycle ......................................................................................71 Data Memory Read Cycle.............................................................................................72 Data Memory Write Cycle.............................................................................................72
19. 20. 21. 22.
TYPICAL APPLICATION CIRCUITS ........................................................................................ 73 PACKAGE DIMENSIONS ......................................................................................................... 75 APPLICATION NOTE ............................................................................................................... 76 REVISION HISTORY ................................................................................................................ 81
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W79E549/W79L549
1. GENERAL DESCRIPTION
The W79E(L)549 is a fast 8051 compatible microcontroller with a redesigned processor core without wasted clock and memory cycles. As a result, it executes every 8051 instruction faster than the original 8051 for the same crystal speed. Typically, the instruction executing time of W79E(L)549 is 1.5 to 3 times faster than that of traditional 8051, depending on the type of instruction. In general, the overall performance is about 2.5 times better than the original for the same crystal speed. Giving the same throughput with lower clock speed, power consumption has been improved. Consequently, the W79E(L)549 is a fully static CMOS design; it can also be operated at a lower crystal clock. The W79E(L)549 contains In-System Programmable (ISP) 32 KB bank-addressed Flash EPROM; 4KB auxiliary Flash EPROM for loader program; on-chip 1 KB MOVX SRAM; power saving modes.
2. FEATURES
8-bit CMOS microcontroller High speed architecture of 4 clocks/machine cycle Pin compatible with standard 80C52 Instruction-set compatible with MCS-51 Seven 8-bit I/O Ports; Port 0 has internal pull-up resisters enabled by software One extra 4-bit I/O port, chip select Three 16-bit Timers 7 interrupt sources with two levels of priority On-chip oscillator and clock circuitry One enhanced full duplex serial port 32KB In-System Programmable Flash EPROM 4KB Auxiliary Flash EPROM for loader program (LDFlash) 256 bytes scratch-pad RAM 1 KB on-chip SRAM for MOVX instruction Programmable Watchdog Timer 6 channels of 8 bit PWM Software Reset Software programmable access cycle to external RAM/peripherals Code protection Packages: − PLCC 68: W79E549A40PN, W79L549A25PN − Lead Free (RoHS)PLCC 68: W79E549A40PL, W79L549A25PL
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Publication Release Date: December 11, 2005 Revision A1
W79E549/W79L549
DEVICE
OPERATING FREQUENCY
OPERATING VOLTAGE
PACKAGE NOMAL LEAD FREE(ROHS)
W79E549 W79L549
up to 40MHz up to 25MHz
4.5V ~ 5.5V 3.0V ~ 5.5V
PLCC68 PLCC68
PLCC68 PLCC68
3. PIN CONFIGURATIONS
T2EX, PWM1, P1.1
T2, PWM0, P1.0
PWM5, P1.5
PWM4, P1.4
PWM3, P1.3
PWM2, P1.2
AD0, P0.0
AD1, P0.1
AD2, P0.2
P7.7
P7.6
P7.5
P7.4
P1.7 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
P1.6 8
P4.2
VDD
6
66
65
64
63
62
61
7
5
4
3
2
1
68
67
P 5.0 P 5.1 P 5.2 P 5.3 RST P 5.4 P 5.5 P 5.6 P 5.7 R X D , P 3.0 P 4.3 TX D , P 3.1 IN T 0, P 3.2 IN T 1, P 3.3 T0, P 3.4 T1, P 3.5 W R , P 3.6
60 59 58 57 56 55 54
P 0.3, A D 3 P 0.4, A D 4 P 0.5, A D 5 P 0.6, A D 6 P 0.7, A D 7 P 6.7 P 6.6 P 6.5 P 6.4 EA P 4.1 A LE PSEN P 2.7, A 15 P 2.6, A 14 P 2.5, A 13 P 2.4, A 12
P LC C 68-pin
53 52 51 50 49 48 47 46 45 44
28 XTAL2
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
P3.7, RD
XTAL1
VSS
P4.0
P7.0
P7.1
P7.2
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P7.3
P6.0
P6.1
P6.2
P6.3
P2.0, A8
P2.1, A9
P2.2, A10
P2.3, A11
W79E549/W79L549
4. PIN DESCRIPTION
SYMBOL TYPE DESCRIPTIONS
EA
I
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of external ROM. It should be kept high to access internal ROM. The ROM address and data will not be present on the bus if EA pin is high and the program counter is within 32 KB area. Otherwise they will be present on the bus. PROGRAM STORE ENABLE: PSEN enables the external ROM data onto the Port 0 address/data bus during fetch and MOVC operations. When internal ROM access is performed, no PSEN strobe signal outputs from this pin. ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates the address from the data on Port 0. RESET: A high on this pin for two machine cycles while the oscillator is running resets the device. CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an external clock. CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1. GROUND: Ground potential POWER SUPPLY: Supply voltage for operation. PORT 0: Port 0 is an open-drain bi-directional I/O port. This port also provides a multiplexed low order address/data bus during accesses to external memory. Port 0 has internal pull-up resisters enabled by software. PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have alternate functions which are described below:
PSEN
O
ALE RST XTAL1 XTAL2 VSS VDD P0.0 − P0.7
O I I O I I I/O
P1.0 − P1.7
I/O
T2(P1.0): Timer/Counter 2 external count input T2EX(P1.1): Timer/Counter 2 Reload/Capture/Direction control PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides the upper address bits for accesses to external memory.
P2.0 − P2.7
I/O
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Publication Release Date: December 11, 2005 Revision A1
W79E549/W79L549
Pin Description,
