i2Chip W3100A

i2Chip W3100A www.i2Chip.com Technical Datasheet v1.1 Description G The i2Chip W3100A is an LSI of hardware protocol stack that provides an easy, low-cost solution Features 6/Hardware Internet protocols included: TCP, IP Ver.4, UDP, ICMP, ARP 6/Hardware Ethernet protocols included: DLC, MAC 6/Supports 4 independent connections simultaneously 6/Internal ICMP responds to PING commands 6/Protocol processing speed: full-duplex 4~5 Mbps 6/Intel/Motorola MCU bus Interface 6/I C Interface 6/Standard MII Interface for under-layer physical chip 6/Socket API support for easy application programming 6/Supports full-duplex mode 6/Internal 16Kbytes Dual-port SRAM for data buffer 6/0.35 µm CMOS technology 6/Wide operating voltage: 3.3V internal operation, 5V tolerant 3.3V IOs 6/Small 64 Pin LQFP Package 2 Description for high-speed Internet connectivity for digital devices Features by allowing simple installation of TCP/IP stack in the Block Diagram hardware. G The W3100A offers system designers a quick, Implementing this LSI into a system easy way to add Ethernet networking functionality to any product. can completely offload Internet connectivity and processing standard protocols from the system, thereby significantly reducing the software development cost. The W3100A contains TCP/IP Protocol Stacks such as TCP, UDP, IP, ARP and ICMP protocols, as well as Ethernet protocols such as Data Link Control and MAC protocol. The W3100A offers a socket API (Application Programming Interface) that is similar to the windows socket API. The chip offers Intel and Motorola 2 Block Diagram MODE0 MODE1 MODE2 MCU (8051, i386, 6811 tested) bus interface and I C for upper-layer and supports standard MII interface for under-layer Ethernet. The W3100A can be applied to handheld devices including Internet phones, VoIP SOC chips, Internet MP3 players, handheld medical devices, LAN cards for Web servers, cellular phones and many other nonportable electronic devices such as large consumer electronic products.G Protocol Engine ICMP TCP UDP MCU Interface IP DLC MAC ARP SCL SDA CLOCK EXT_CLK RESET MII Interface ~p•Œ›GšGyhwpkGOyŒœšˆ‰“ŒGh——“Šˆ›–•Tš—ŒŠŠGp•›Œ““ŒŠ›œˆ“Gw™–—Œ™› GkŒŒ“–—Œ™PH/ RX_CLK RXDV/CRS RXD(3:0) TX_CLK TXE TXD(3:0) COL /SERIAL /FDPLX /LINK : DPRAM /CS /WR /RD /INT ADDR(14:0) DATA(7:0) Table of Contents G G G G G G G kŒšŠ™—›–• UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU XG mŒˆ›œ™ŒšUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU XG i“–Š’GkˆŽ™ˆ” UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU XG w•GhššŽ•”Œ•›UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU ZG zŽ•ˆ“GkŒšŠ™—›–• UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU [G yŒŽš›Œ™GkŒ•›–•šUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU XXG XUGj–•›™–“GyŒŽš›Œ™š UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU XXG YUGz š›Œ”GyŒŽš›Œ™šUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU X]G ZUGw–•›Œ™GyŒŽš›Œ™šUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU X_G [UGjˆ••Œ“GyŒŽš›Œ™š UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU YWG G G p•›Œ™•ˆ“GtŒ”–™ Gˆ•‹GyŒŽš›Œ™š UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU YZG kŒšŠ™—›–•G–Gmœ•Š›–•šUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU YG XUGp•›ˆ“¡ˆ›–•G–G~ZXWWhUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU YG YUG{jwGw™–›–Š–“ UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU YG ZUG|kwGw™–›–Š–“ UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU ZYG [UGpwGsˆ Œ™Gyh~Gt–‹ŒUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU ZG UGthjGsˆ Œ™Gyh~Gt–‹Œ UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU Z]G G h——“Šˆ›–•Gp•–™”ˆ›–•UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU [WG XUGyŒ“ˆ›–•š—G‰Œ›žŒŒ•Gtj|GiœšGpVmGt–‹ŒGˆ•‹Gt–‹ŒG—•GOt‚YaW„P UUUUUUUUUUUUUUUUUUUUUUUUUUUU [WG YUGk™ŒŠ›GiœšGpVmGt–‹ŒU UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU [XG ZUGp•‹™ŒŠ›GiœšGpVmGt–‹ŒU UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU [XG [UGp jGpVmGt–‹ŒUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU [ZG UGw šŠˆ“Gsˆ Œ™Gp•›Œ™ˆŠŒUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU [_G G {”•ŽGkˆŽ™ˆ”š UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU WG XUGj“–Š’Œ‹G”–‹ŒOjsvjrGdGYto¡P UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU WG YUGlŸ›Œ™•ˆ“GŠ“–Š’Œ‹G”–‹ŒOl{†jsrGdGWto¡P UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU YG ZUGu–•TŠ“–Š’Œ‹G”–‹ŒOjsvjrGdGYto¡P UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU [G [UGp jG”–‹ŒOjsvjrGdGYto¡PUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU ^G UGtŒ‹ˆGp•‹Œ—Œ•‹Œ•›Gp•›Œ™ˆŠŒGOtppP UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU `G G G G G wˆŠ’ˆŽŒGkŒšŠ™—›–• UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU ]XG h——Œ•‹ŸGhUG G l“ŒŠ›™Šˆ“Gz—ŒŠŠˆ›–•šUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU ]YG ; ; ~p•Œ›GšGyhwpkGOyŒœšˆ‰“ŒGh——“Šˆ›–•Tš—ŒŠŠGp•›Œ““ŒŠ›œˆ“Gw™–—Œ™› GkŒŒ“–—Œ™PHG Y Pin Assignment G Figure 1: 64-Pin LQFP Pin Assignments TX_CLK MODE0 TXD[3] TXD[2] TXD[1] 50 64 RESET VCC GND CLOCK A[14]/DA[6] A[13]/DA[5] A[12]/DA[4] A[11]/DA[3] A[10]/DA[2] A[9]/DA[1] A[8]/DA[0] VCC GND A[7] A[6] A[5] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 A[4] 63 62 61 60 59 58 57 56 55 54 53 52 51 49 48 47 46 45 44 43 42 41 COL MODE1 RX_CLK GND RXDV/CRS RXD[3] RXD[2] RXD[1] RXD[0] VCC VCC GND /LINK /SERIAL /FDPLX EXT_CLK TXD[0] 40 39 38 37 36 35 34 33 32 D[0] GND GND 27 D[4] VCC SDA i2Chip W3100A 64-LQFP 18 A[3] 19 A[2] 20 A[1] 21 A[0] 22 VCC 23 GND 24 D[7] 25 D[6] 26 D[5] 28 MODE2 TXE /WR SCL /INT /RD /CS 29 D[3] 30 D[2] 31 D[1] G G ~p•Œ›GšGyhwpkGOyŒœšˆ‰“ŒGh——“Šˆ›–•Tš—ŒŠŠGp•›Œ““ŒŠ›œˆ“Gw™–—Œ™› GkŒŒ“–—Œ™PHG Z Signal Description Table 1: W3100A MII Signal Description PIN# 52 51 50 49 53 Signal TXD[3] TXD[2] TXD[1] TXD[0] TXE I/O O Description TRANSMIT DATA: Nibble/Serial NRZ data output to the ENDEC that is valid on the rising edge of TX_CLK. In serial mode, the TXD[0] pin is used as the serial data pin, and TXD[3:1] are ignored. O TRANSMIT ENABLE: becomes active when the first nibble/serial data of the packet is valid on TXD[3:0] and goes low after the last nibble/serial data of the packet is clocked out of TXD[3:0]. signal connects directly to the ENDEC (PHY device). is active high. This This signal 55 TX_CLK I TRANSMIT CLOCK: TX_CLK is sourced by the PHY. TX_CLK is 2.5 MHz in 10BASE-T Nibble mode, and 25 MHz in 100BASE-T Nibble mode. 43 42 41 40 44 RXD[3] RXD[2] RXD[1] RXD[0] RXDV/CRS I RECEIVE DATA: Nibble wide receive data (synchronous to RX_CLK) that must be driven on the falling edge of RX_CLK. In serial mode, the RXD[0] pin is used as the data input pin which is also clocked in on the falling edge of RX_CLK. and become don’t cares. RXD[3:1] pins I CARRIER SENSE: signal provided by the ENDEC and indicates that carrier is present. This signal is active high. 46 48 RX_CLK COL I I RECEIVE CLOCK: Re-synchronized clock from the ENDEC and indicates that carrier is present. COLLISION DETECT: becomes active when a collision has been detected in Half Duplex modes. This signal is asynchronous, active high and ignored during fullduplex operation. Table 2: W3100A MCU Interface Signal Description PIN# 5-11 Signal A[14-8] / DA[6-0] I/O I Description ADDRESS PINS / DEVICE ADDRESS PINS Used as Address[14 – 8] pin when set in MCU Bus Interface mode. Used as Device address[6 – 0] pin for I C Interface when set in 2 I C Interface mode. 14-21 24-27 29-32 61 A[7-0] D[7-4] D[3-0] /INT O INTERRUPT: Indicates that the W3100A requires MCU attention after reception or transmission. The interrupt is cleared by writing to the ISR (Interrupt Status Register). 64 /CS I All interrupts are maskable by writing IMG (Interrupt Mask Register). This signal is active low. CHIP SELECT: This signal is active low. I I/O ADDRESS PINS DATA PINS 2 ~p•Œ›GšGyhwpkGOyŒœšˆ‰“ŒG