W3000 PLL Dual-Band Frequency Synthesizer

Advance Data Sheet December 1999 W3000 PLL Dual-Band Frequency Synthesizer Features + + + + + + + + + Applications + + + + + 2.2 GHz operational Dual-band optimized Low supply current (5.1 mA) Surface-mount 14-pin TSSOP package Scaled PD gain for dual-band operation Programmable phase-detector polarity Synchronous or forced counter update loading Powerdown mode via external pin or serial bus Low-load capacitance on reference input buffer GSM900/1800/1900 North American IS-136/137 Personal Digital Cellular (Japan RCR-27) Personal Handy Phone (Japan RCR-28) CDMA (IS-95) LD REF_IN R 11-BIT COUNTER TCXO IPD SETTING PD POLARITY IREF M 11-BIT COUNTER PHASE DETECTOR VDDC VCP VCO BAND A VCO BAND B PRESCALER ÷64/65 A 7-BIT COUNTER MAIN_IN IREF HIGH-PRECISION CURRENT REFERENCE RREF VDDC OFF CHIP IPD SETTING PD POLARITY BAND CONTROL LOGIC 24-BIT SERIAL SHIFT REGISTER LAT DAT CLK Figure 1. Block Diagram with Pinout W3000 PLL Dual-Band Frequency Synthesizer Advance Data Sheet December 1999 Table of Contents Features...............................................................................................................................................................1 Applications .........................................................................................................................................................1 Description...........................................................................................................................................................3 Pin Information.....................................................................................................................................................4 Absolute Maximum Ratings..................................................................................................................................5 Electrostatic Discharge Caution............................................................................................................................5 Electrical Characteristics ......................................................................................................................................6 Charge Pump Current ..........................................................................................................................................7 PLL Programming Information .............................................................................................................................8 Serial Data Input ..................................................................................................................................................9 Serial Bus Timing Information ..............................................................................................................................9 Functional Descriptions ......................................................................................................................................10 REF Register .....................................................................................................................................................11 MAIN Register....................................................................................................................................................15 PLL Lock-Detect Function ..................................................................................................................................17 Typical Performance Characteristics ..................................................................................................................17 MAIN_IN Input Parallel Equivalent Circuit.......................................................................................................18 Application Example ..........................................................................................................................................18 Application Information ......................................................................................................................................19 Typical Performance Data..................................................................................................................................22 Outline Diagram.................................................................................................................................................26 14-Pin TSSOP................................................................................................................................................26 Manufacturing Information .................................................................................................................................27 Ordering Information ..........................................................................................................................................27 2 Lucent Technologies Inc. Advance Data Sheet December 1999 W3000 PLL Dual-Band Frequency Synthesizer Description The W3000 is a high-performance UHF RF PLL synthesizer, designed for use in digital wireless communication applications. Particular emphasis in the design has been placed on dual-band applications, with near-seamless switching between operational bands without the need for external loop-filter circuitry other than that required for single band applications. In combination with a suitable reference crystal, UHF VCO, and associated loop-filter components, the W3000 offers a very low-noise oscillator solution. The reference signal is divided by a programmable 11-bit counter to provide a wide range of comparison frequencies, allowing compliance with the various standards. The reference input is rising-edge triggered, and we recommend that an inverting buffer be used when the W3000 is interfaced to a commercial TCXO. The MAIN_IN signal normally associated with the UHF VCO is fed into a dual modulus prescaler (64/65) and is then divided by the 11-bit main counter to be compared to the output of the reference counter in a digital phase detector. The W3000 is implemented with programmable charge-pump currents to allow fast switching between bands for dual-band applications, without changing the loop filter. The charge pump can be programmed internally, or externally with a resistor (recommended). Charge pump outputs can be disabled, thereby allowing open-loop VCO modulation schemes. With synchronous reloading, the counter reloads a new programmed value when the counter reaches zero. With forced counter reloading, the reloading occurs when the programmed word is latched in. These techniques can improve lock time when performing a dual-band hop or in start-up conditions. The W3000 uses a standard 3-wire programming bus (data, enable, clock) that operates up to 10 MHz. This serial interface is via a 24-bit word that incorporates both register addressing and device addressing allowing two chips to share the bus. TR REGISTER ADDRESS DECODER CONFIG REGISTER MAIN REGISTER A[0:2] W3020 SC1 LAT CLK SERLE1 SERCK SERDA PARALLEL LATCH SERIAL SHIFT DAT DAT SERIAL SHIFT CLK LAT W3000 PARALLEL LATCH A[0:2] ADDRESS DECODER MAIN REGISTER REF REGISTER Figure 2. Serial Bus Programming Lucent Technologies Inc. 3 W3000 PLL Dual-Band Frequency Synthesizer Advance Data Sheet December 1999 Pin Information VDDC CPOUT VSS1 VSS2 MAIN_IN VDD1 VDD2 1 2 3 4 5 6 7 14 13 12 11 10 9 8 LAT DAT CLK PWRDN REF_IN RES LOCKDET Figure 3. Pin Diagram Table 1. Pin Descriptions Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Symbol VDDC CPOUT VSS1 VSS2 MAIN_IN VDD1 VDD2 LOCKDET RES REF_IN PWRDN CLK DAT LAT Function Supply Output Ground Ground Input Supply Supply Output Input Input Input Input Input Input Charge Pump Output. Ground 1. Charge pump and logic ground. Ground 2. Prescaler and reference ground. VCO Signal Input. Must be ac-coupled. Voltage Supply 1. Prescaler supply voltage. Voltage Supply 2. Logic and reference supply (must be equal to VDD1). Lock Detect Output. External Resistor Input. Add resistor to VDDC if required (>10 kΩ). Reference Frequency Input. Connection from reference oscillator. Must be accoupled. Powerdown. For low current operation. (Low is powerdown mode.) Serial Input. Programming clock line. Serial Input. Programming data line. Serial Input. Programming latch line. Name/Description Charge Pump Positive Supply Voltage. Must be ≥VDD. (VDD = VDD1 = VDD2). 4 Lucent Technologies Inc. Advance Data Sheet December 1999 W3000 PLL Dual-Band Frequency Synthesizer Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Parameter Ambient Operating Temperature Storage Temperature Lead Temperature (soldering, 10 s) Positive Supply Voltage Positive Charge Pump Supply Voltage Power Dissipation ac Input Voltage Digital Voltages Symbol TA Tstg TL VDD VDDC PD — — Min –30 –65 — 0 0 — 0 Vss – 0.3 Max 85 150 300 4.5 4.5 250 VDD VDD + 0.3 Unit °C °C °C Vdc Vdc mW Vp-p Vdc Electrostatic Discharge Caution Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. Lucent Technologies Microelectronics Group employs a human-body model (HBM) and a charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define the model. No industry-wide standard has been adopted for CDM. However, a standard HBM (resistance = 1500 Ω, capacitance = 100 pF) is widely used and, therefore, can be used for comparison purposes. Parameter ESD Threshold Voltage ESD Threshold