34x34 Crosspoint Switch

www.DataSheet4U.com VITESSE SEMICONDUCTOR CORPORATION Datasheet VSC835 Features • 34 Input by 34 Output Crosspoint Switch • 2.5 Gbits/sec. NRZ Data Bandwidth • TTL Compatible µP Interface • Differential PECL Data Inputs • On-chip 50Ω Input Terminations 2.5 Gbits/sec 34x34 Crosspoint Switch with Signal Detection • 50Ω Source Terminated PECL Output Drivers • Single 3.3V Supply • 14W Maximum Power Dissipation • High Performance 256 BGA Package General Description The VSC835 is a monolithic 34x34 asynchronous crosspoint switch, designed to carry broadband data streams at up to 2.5 Gbit/s. The non-blocking switch core is programmed through a parallel port interface that allows random access programming of each output port. A high degree of signal integrity is maintained through the chip through fully differential signal paths. The crosspoint function is based on a multiplexer tree architecture. Each data output is driven by a 34:1 multiplexer tree that can be programmed to one and only one of its 34 inputs, and each data input can be routed to multiple outputs. The signal path is unregistered, so no clock is required for the data inputs. The signal path is asynchronous, so there are no restrictions on the phase, frequency, or signal pattern at each input. Each input channel and each output channel has an signal monitor function that can be used to identify loss of activity (LOA). An interrupt pin is provided to signal LOA, after which an external controller can query the chip to determine the channel(s) on which the fault occurred. Each output driver is a fully differential switched current driver with on-die back-terminations for maximum signal integrity. Data inputs are terminated on die through 50 ohm resistors terminated to VTERM. The parallel interface uses TTL levels, and provides address, data, and control pins that are compatible with a microprocessor-style interface. The control port provides access to all chip functions, including LOA and programming. Program buffering is provided to allow multiple program assignments to be queued and issued simultaneously via a single configure command. VSC835 Block Diagram A0 Y0 A33 Control Logic µP interface Y33 G52270-0, Rev. 4.1 7/24/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 1 VITESSE SEMICONDUCTOR CORPORATION 2.5 Gbits/sec 34x34 Crosspoint Switch with Signal Detection Figure 1: Detailed Block Diagram Datasheet VSC835 A,AN[33:0] 34 x 34 switch core LOA monitor 34 output drivers Y,YN[33:0] Program memory Control interface DATA[5:0], ADDR[5:0] ALE, CSB, WRB, RDB INTB, MONCLK, CONFIG Functional Description Data Paths All input data must be differential and biased to PECL levels. On-chip terminations are provided, with a nominal impedance of 50 ohms. All input termination resistors are tied to VTERM. Data outputs are provided through differential current switches with on-chip terminations that produce a PECL level output swing. The drive level of the output circuit is designed to produce standard PECL levels when terminated in 50 ohms to 2.0 volts. Other termination voltages are possible, such as to VCC or 1.3 volts, but the voltage level of the output will be shifted from its nominal value. The common-mode voltage of the output swing can be adjusted using the VCOM pins. The adjustment range is not calibrated, but typically allows for +/- 200mV of adjustment in common-mode voltage. The VCOM pin self-biases to a nominal value when left unconnected. Output channels can be powered off in pairs if fewer than 34 outputs are required. By connecting the VEE pin associated with a given pair of outputs to VCC, the output pairs will pull to VCC and chip power will be reduced by approximately 300mW per pair. Page 2 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52270-0, Rev. 4.1 7/24/00 VITESSE SEMICONDUCTOR CORPORATION Datasheet VSC835 2.5 Gbits/sec 34x34 Crosspoint Switch with Signal Detection Programming Interface The switch core is programmed through a parallel interface circuit that allows random reads or writes to the program memory array. The program memory array is buffered to allow multiple programming instructions to be loaded simultaneously with the CONFIG pin. Parallel programing can be clocked at up to a 50MHz rate and state read-back can be performed at up to 25MHz. The program data is composed of two parts: output address and input address. The output address, denoted by ADDR[5:0], specifies which output channel is to be programmed. The input address, denoted by DATA[5:0], specifies which input port the switch slice should connect to. The format of the program data is simple binary. For example: ADDR[5:0] (000100) / DATA[5:0] (000110) would direct output channel Y4 to connect to input channel A6. The programming state may be verified (read back) by applying the address of the desired output and asserting RDB. The programming state is unknown at power-on. Additional address space is provided for access to the monitor registers (see sections below). The microprocessor interface consists of the following signals. Levels are TTL (see DC Characteristics) : Table 1: Programming Interface Signal Table Pin D[5:0] A[5:0] ALE CSB WRB RDB INTB I/O B I I I I I O Description Bidirectional data bus to transfer data to/from internal program registers Address bus to select internal program registers for read-write operations ALE functionality is not implemented at this time. Tie this pin High. Chip Select (Active Low): assert this pin whenever the part is being read or programmed. Write (Active Low): program data will be transferred to the first level internal registers on the rising edge of this signal (when CSB is also low). Read (Active Low): program data from the internal program or monitor registers will be read out on the data bus when this signal goes low (with CSB also low). Interrupt (Active Low): this signal is asserted when an LOA condition is found Configure (Active High): assert this signal to transfer queued program information from the first-level internal registers to the second-level registers, making the programming take effect. This signal may be tied high to leave the second-level registers transparent so all programming will take effect immediately. CSB must be active (low) when CONFIG is asserted. CONFIG may be tied to a highorder bit of the address bus Monitor states are transferred to monitor registers on the rising edge of this signal. MONCLK is not expected to exceed 3MHz. CONFIG I MONCLK I Loss of Activity (LOA) Monitoring The LOA function consists of an activity monitor on each input channel, connected directly to the pads. The state of a monitor (whether or not it has been toggled by an input transition) can be observed by applying the address1 of the monitor register corresponding to the signal of interest and asserting RDB. Each monitor register is four bits in length, covering the state of four inputs. There is one extra two-bit monitor for the 33rd and 34th inputs. The state of each monitor is transferred to the register on the rising edge of MONCLK, whereupon the activity monitor is cleared until more activity is detected. 1. See Memory Map Table G52270-0, Rev. 4.1 7/24/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 3 VITESSE SEMICONDUCTOR CORPORATION 2.5 Gbits/sec 34x34 Crosspoint Switch with Signal Detection Datasheet VSC835 If any change in a monitor state occurs after sampling by MONCLK, an interrupt will be signalled by asserting INTB, and the user must identify the offending channel by reading the monitor states. The interrupt will be cleared when the corresponding activity monitor is read, but the monitor state will not be changed. If multiple monitors have triggered the interrupt, it will persist until all the corresponding monitors have been read. LOA requires a minimum signal level of 30-150mV peak-peak to recognize an input as active. This is required to distinguish noise on an unconnected signal (where both inputs float to the termination voltage) from activity on a live signal. A minimum of two transitions defines activity. The threshold signal level is controlled by the voltage on the VHYS pin. In order to keep the hysteresis in a useful range, it is recommended that VHYS be nominally tied to VCC (useful range is 2.0V to VCC ). . Table 2: Memory Map Address 00h 01h ... 21h 22h, 23h 24h, 25h 26h, 27h 28h, 29h 2Ah Access R/W R/W ... R/W R/O R/O R/O R/O R/O Description Output Y0’s programmed input channel (write and then assert CONFIG to program) Output Y1’s programmed input channel ... Output Y33’s programmed input channel Rx Signal monitor for inputs [A0-A3], [A4-A7] (Logic ‘1’=No activity) Rx Signal monitor for inputs [A8-A11], [A12-A15] Rx Signal monitor for inputs [A16-A19], [A20-A23] Rx Signal monitor for inputs [A24-A27], [A28-A31] Rx Signal monitor for inputs [A32-A33] AC Characteristics Table 3: Data Path Parameter FRATE TISKW TOSKW tR, tF tR, tF tjP Data rate Input channel delay skew (1) Output channel delay skew (2) High-speed input rise/fall times, 20% to 80% (3) High-speed output rise/fall times, 20% to 80% Output data eye jitter, peak-peak, 231 PRBS (4) Description Min - Typ 300 300 - Max 2.5 150 150 100 Units Gbits/s ps ps ps ps ps note: Unless otherwise stated, all specifications are guaranteed but not tested. note 1: Skew between any two input channels to a given output. note 2: Skew between any two output channels from the same input channel. note 3: Required for high-speed output rise/fall spec at FRATE=2.5 Gbits/s. For lower rate signals, use 0.375/FRATE note 4: Broadband jitter added to a jitter-free signal; jitter is primarily in the form of ISI for random data Page 4 © VITESSE SEMICONDUCTOR CORPORATION