2.5Gb/s 17 x 17 Crosspoint Switch

www.DataSheet4U.com VITESSE SEMICONDUCTOR CORPORATION Datasheet VSC834 Features • 17 Input by 17 Output Crosspoint Switch • 2.5Gb/s NRZ Data Bandwidth • 42 Gb/s Aggregate Bandwidth • TTL Compatible µP Interface • Differential PECL Data Inputs 2.5Gb/s 17x17 Crosspoint Switch with Input Signal Activity (ISA) Monitoring • On-chip 50Ω Input Terminations • 50Ω Source Terminated PECL Output Drivers • Single 3.3V Supply • 9W Maximum Power Dissipation • High Performance 256 Pin BGA Package General Description The VSC834 is a monolithic 17x17 asynchronous crosspoint switch designed to carry broadband data streams at up to 2.5Gb/s. The non-blocking switch core is programmed through a parallel microprocessor interface that allows random access programming of each output port. A high degree of signal integrity is maintained through the chip through fully differential signal paths. The crosspoint function is based on a multiplexer tree architecture. Each data output is driven by a 17:1 multiplexer tree that can be programmed to one and only one of its 17 inputs, and each data input can be programmed to multiple outputs. The signal path is unregistered, so no clock is required for the data inputs. The signal path is asynchronous, so there are no restrictions on the phase, frequency, or signal pattern at each input. Each input channel has an activity monitor function that can be used to identify loss of activity (LOA). An interrupt pin is provided to signal LOA, after which an external controller can query the chip to determine the channel(s) on which the fault occurred. Each output driver is a fully differential switched current driver with on-die back-terminations for maximum signal integrity. Data inputs are terminated on die through 50Ω resistors connected to VTERM. The parallel interface uses TTL levels, and provides address, data, and control pins that are compatible with a microprocessor-style interface. The control port provides access to all chip functions, including LOA, and programming. Program buffering is provided to allow multiple program assignments to be queued and issued simultaneously via a single configure command. VSC834 Block Diagram A0 Y0 A16 Control Logic µP Interface Y16 G52247-0, Rev 4.2 02/09/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 1 VITESSE SEMICONDUCTOR CORPORATION 2.5Gb/s 17x17 Crosspoint Switch with Input Signal Activity (ISA) Monitoring Figure 1: Detailed Block Diagram: Datasheet VSC834 A, AN[16:0] LOA Monitor 17 Program Memory Output Drivers 17x17 Switch Core Y, YN[16:0] Control Interface DATA[4:0], ADDR[5:0] ALE, CSB, WRB, RDB INTB, MONCLK, CONFIG Functional Description Data Paths All input data must be differential and biased to PECL levels. On-chip terminations are provided, with a nominal impedance of 50Ω. All input termination resistors are tied to VTERM. Data outputs are provided through differential current switches with on-chip terminations that produce a PECL level output swing. The drive level of the output circuit is designed to produce standard PECL levels when terminated in 50Ω to 2.0V. Other termination voltages are possible, such as to VCC or 1.3V, but the voltage level of the output swing will be shifted from its nominal value. The common-mode voltage of the output swing can be adjusted using the VCOM pin. The adjustment range is not calibrated, but typically allows for about +200mV of adjustment in the output common-mode voltage. Output channels can be powered off in pairs if fewer than 17 outputs are required. By connecting the VEE pin associated with a given pair of outputs to VCC, the output pairs will pull to VCC and chip power will be reduced by roughly 200mW. Page 2 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52247-0, Rev 4.2 02/09/01 VITESSE SEMICONDUCTOR CORPORATION Datasheet VSC834 2.5Gb/s 17x17 Crosspoint Switch with Input Signal Activity (ISA) Monitoring Programming Interface The switch core is programmed through a parallel interface circuit that allows random reads or writes to the program memory array. The program memory array is buffered to allow multiple programming instructions to be loaded simultaneously with the CONFIG pin. Parallel programing can be clocked at up to a 50MHz rate. The program data is composed of two parts: output address and input address. The output address, denoted by ADDR[5:0], specifies which output channel is to be programmed. The input address, denoted by DATA[4:0], specifies which input port the switch slice should connect to. The format of the program data is simple binary, where the binary value maps directly to the switch slice position and/or input port number. For example: ADDR[5:0] (000100) / DATA[4:0] (00110) would direct output channel Y4 to connect to input channel A6. The programming state may be verified (read back) by applying the address of the desired output and asserting RDB. The programming state is unknown at power-on. Additional address space is provided for access to the monitor registers (See Table 2). The microprocessor interface consists of the following signals. Levels are TTL (see Table 6). Table 1: Signal Table Pin D[5:0] A[5:0] ALE CSB WRB RDB INTB I/O B I I I I I O Description Bidirectional data bus to transfer data to/from internal program registers Address bus to select internal program registers for read-write operations Address Latch Enable: for use with multiplexed address/data buses. Latches the address bus internally when low. Chip Select (Active Low): assert this pin whenever the part is being read or programmed. Write (Active Low): program data will be transferred to the first level internal registers on the rising edge of this signal (when CSB is also low). Read (Active Low): program data from the internal program or monitor registers will be read out on the data bus when this signal goes low (with CSB also low). Interrupt (Active Low): this signal is asserted when an LOA condition is found Configure (Active High): assert this signal to transfer queued program information from the first-level internal registers to the second-level registers, making the programming take effect. This signal may be tied high to leave the second-level registers transparent so all programming will take effect immediately. CSB must be active (low) when CONFIG is asserted. CONFIG may be tied to a highorder bit of the address bus Monitor states are transferred to monitor registers on the rising edge of this signal. MONCLK is not expected to exceed 3MHz. CONFIG I MONCLK I Loss of Activity (LOA) Monitoring The LOA function consists of an activity monitor on each input channel, connected directly to the pads. The state of a monitor (whether or not it has been toggled by an input transition) can be observed by applying the address (See Table 2) of the monitor register corresponding to the signal of interest and asserting RDB. Each monitor register is four bits in length, covering the state of four inputs or outputs. There is one extra one-bit monitor for each of the 17th input and 17th output. The state of each monitor is transferred to the register periodically on the rising edge of MONCLK, whereupon the activity monitor is clered until more activity is detected. G52247-0, Rev 4.2 02/09/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 3 VITESSE SEMICONDUCTOR CORPORATION 2.5Gb/s 17x17 Crosspoint Switch with Input Signal Activity (ISA) Monitoring Datasheet VSC834 If any change in a monitor state occurs after sampling by MONCLK, an interrupt will be signalled by asserting INTB, and the user must identify the offending channel by reading the monitor states. The interrupt will be cleared when the corresponding activity monitor is read, but the monitor state will not be changed. If multiple monitors have triggered the interrupt, it will persist until all the corresponding monitors have been read. The LOA circuitry requires a minimum signal level of 30-150 mV peak-peak to recognize an input as active. This is required to distinguish noise on an unconnected signal (where both inputs float to the termination voltage) from activity on a live signal. A minimum of two transitions defines activity. The threshold signal level can be adjusted with the VHYS pin, which can set the threshold from zero to the maximum allowed input swing. The VHYS pin will self-bias to a nomial value that will be appropriate for most applications (30-150mV p-p input level). Although uncalibrated for nominal level, gain and linearity, the VHYS pin can be externally set to adjust the threshold level over the entire range of the input signal, from zero to the maximum level allowed at the input. Table 2: Memory Map Address 00h 01h ... 10h 11h ... 20h 21h 22h 23h 24h 25h Access R/W R/W ... R/W R/W ... R/W R/O R/O R/O R/O R/O Output Y1’s programmed input channel ... Output Y16’s programmed input channel Description Output Y0’s programmed input channel ( write and then assert CONFIG to program) Internal output Y17’s programmed input channel ... Internal output Y32’s programmed input channel Rx Activity monitor for inputs A0, A1,A2,A3 Rx Activity monitor for inputs A4, A5,A6,A7 Rx Activity monitor for inputs A8, A9,A10,A11 Rx Activity monitor for inputs A12, A13,A14,A15 Rx Activity monitor for input A16 ( Logic ‘1’=No activity) Page 4 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52247-0, Rev 4.2 02/09/01 VITESSE