2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch

www.DataSheet4U.com VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC830 Features • Dual 2x2 Crosspoint Switch • 2.7Gb/s NRZ Data Bandwidth, 2.7GHz Signal Bandwidth • PECL/TTL-Compatible Control Inputs • PECL-Compatible High-Speed I/O 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch • 50Ω Source Terminated Output Driver and Programmable Input Terminations • Single 3.3V Supply, 1W Typical Dissipation • Power-Down Capability for Unused Outputs • Compact 44-Pin PQFP, 10x10mm Package General Description The VSC830 is a monolithic dual 2x2 asynchronous crosspoint switch, designed for critical signal path control and buffering applications, such as loop-back, protection switching, and multi-channel backplane driver/receivers. Signal path delay is tightly matched between each output channel to eliminate the need for delay path compensation when switching between signal sources. The crosspoint function is based on a multiplexer tree architecture. Each 2x2 switch can be considered as a pair of 2:1 multiplexers that share the same inputs. The signal path through each switch is fully differential and delay matched. The signal path is unregistered, so there are no restrictions on the phase, frequency, or signal pattern at each input. Unused outputs can be independently powered off, thereby eliminating power on unused sections (see Design Guide section in this data sheet). The switch control inputs can be configured to be compatible with PECL or TTL levels. The high-speed input and output levels are nominally PECL compatible and capable of interfacing with a wide range of termination schemes. VSC830 Symbol Diagram S1,S2 A1 A2 S1,S2 A1 A2 Y1 Y2 Y1 Y2 G52192-0, Rev 4.0 05/23/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 1 VITESSE SEMICONDUCTOR CORPORATION 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch Data Sheet VSC830 Functional Block Diagram PEMODE S1A A1A+ A1ATERM_ENABLE_A SL VCC VCCP1A 0 Y1A Y1AN VEE1A VCCP2A 1 S2A SL A2A+ A2A- 0 Y2A Y2AN VEE2A 1 S1B A1B+ A1BSL VCCP1B 0 Y1B Y1BN VEE1B VCCP2B SL 1 TERM_ENABLE_B S2B 0 A2B+ A2B- Y2B Y2BN VEE2B 1 Page 2 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52192-0, Rev 4.0 05/23/01 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC830 Functional Description 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch Select As shown in Figure 1, each output can be treated as a 2:1 multiplexer, with the A1 and A2 inputs common to both multiplexers. The select input S1 independently controls the state of the multiplexer that drives output Y1, and select input S2 independently controls the output of Y2. Figure 1: Select Functional Block Diagram S1 S2 A1 A2 Y1 Y2 Table 1 specifies the function of the select inputs. Table 1: Select Function S1 0 1 0 1 S2 0 0 1 1 Y1 A1 A2 A1 A2 Y2 A1 A1 A2 A2 MODE The interface level of the select pins, S1 and S2, can be programmed to either TTL or PECL levels by shorting the MODE pin to either VCC or VEE. Note that the MODE pin must be tied to either VCC or VEE. The function of MODE is specified in Table 2. Table 2: MODE Function MODE VEE VCC S1, S2 TTL PECL G52192-0, Rev 4.0 05/23/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 3 VITESSE SEMICONDUCTOR CORPORATION 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch Data Sheet VSC830 Power-Down Power to each output stage is provided through VCC, VCCP, and VEE. VCC is common to all outputs. To power off unused outputs, tie the respective VEE and VCCP pin to VCC, as shown in Figure 2. Figure 2: Power-Down Mode Example VCC VCCP1A VCCP2A VCCP1B VCCP2B VEE1A “ON” VEE2A “ON” VEE1B “OFF” VEE2B “OFF” Minimum power configuration requires output channel 1A active, so power must be applied to VCCP1A and VEE1A at all times. Programmable input termination Across each differential input (from the + input to the - input) of the VSC830 is a switched 100Ω termination resistor. Using the TERM_ENABLE pin, the termination can be optionally disabled. To enable the input termination, connect the respective TERM_ENABLE pin to VCC. To disable the internal termination, connect TERM_ENABLE to VEE. If unconnected, the TERM_ENABLE pin will self-bias to VEE and disable the internal termination. Independent termination controls are provided for the “A” and “B” switches. Page 4 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com G52192-0, Rev 4.0 05/23/01 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC830 AC Characteristics Table 3: AC Timing Symbol FRATE FBW TSKW TCON tR, tF tjP Signal path data rate Signal path bandwidth (-3dB) Channel to channel delay skew Switch configuration setup time(1) High-speed output rise/fall times, 20% to 80% Signal path added jitter, peak-peak(1) 23 (2) 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch Parameter Min Typ Max 2.7 2.7 Units Gb/s GHz ps ns ps ps 50 1 150 40 NOTES: (1) Tested on a sample basis only, with 2 -1 PRBS data, input signal rise/fall time < 150ps. Value stated in table is added to measurement system jitter. (2) Input signal rise/fall time < 150ps, measured using an alternating 1, 0 pattern. DC Characteristics (All characteristics are over the specified operating conditions) Table 4: Power Supply Symbol ICC PD PT Parameter Total VCC(P) supply current Power dissipation per output (Y1A±, Y2A±, Y1B±, Y2B±) Total chip power (all outputs powered on) Min Typ Max 350 300 1.2 Units mA mW W Conditions NOTE: Specified with outputs terminated, 100Ω between true and complement, VCC = 3.45V. Table 5: Select Input Levels—TTL Mode Symbol VIH VIL IIH IIL Parameter Input HIGH voltage (TTL) Input LOW voltage (TTL) Input HIGH current (TTL) Input LOW current (TTL) Min 2.0 Typ Max 0.8 500 -500 Units V V µA µA Conditions VIN = 2.4V VIN = 0.5V Table 6: Select Input Levels—PECL Mode Symbol VIH VIL IIH IIL Parameter Input HIGH voltage (PECL) Input LOW voltage (PECL) Input HIGH current (PECL) Input LOW current (PECL) Min VCC1.0 Typ Max Units V Conditions VCC1.6 500 -500 V µA µA VIN = 2.5V VIN = 1.5V Table 7: Control Inputs Symbol RPEMODE Parameter PEMODE pin impedance Min Typ 3100 Max Units Ω Conditions G52192-0, Rev 4.0 05/23/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 5 VITESSE SEMICONDUCTOR CORPORATION 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch Table 8: “A” Input Levels (Differential PECL) Data Sheet VSC830 Min 200 VCC1.7 Symbol VID VICM Parameter Input differential voltage Input common-mode voltage Typ Max 1000 VCC0.9 Units mV V Conditions See Note 1 NOTE: (1) Peak-to-peak swing of each side of the differential input. Table 9: “Y” Output Levels (Differential PECL) Symbol VOD1 VOD2 VOCM Parameter Output differential voltage (Data) Output differential voltage (Clock) Output common-mode voltage Min 400 400 VCC1.6 Typ 700 550 Max 1000 850 VCC1.0 Units mV mV V Conditions See Note 1 See Note 2 NOTES: (1) Peak-peak swing of each side of the differential output. 223-1 PRBS data. (2) Peak-to-peak swing of each side of the differential output. Alternating 1, 0 pattern. Absolute Maximum Ratings Power Supply Voltage (VCC) Potential to GND ..............................................................................-0.5V to +4.0V TTL Input Voltage Applied ................................................................................................... -0.5V to VCC +0.5V ECL Input Voltage Applied .................................................................................................... -0.5V to VCC +0.5V Output Current (IOUT) .................................................................................................................................... 50mA Case Temperature Under Bias (TC) .............................................................................................-55oC to + 125oC Storage Temperature (TSTG)........................................................................................................-65oC to + 150oC NOTE: (1) Caution: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing permanent damage. Functionality at or exceeding the values listed is not implied. Exposure to these values for extended periods may affect device reliability. Operating Conditions Supply voltage (VEE) .......................................................................................................................................... 0V Supply voltage (VCC) ............................................................................................................................ +3.3V ±5% Supply voltage (VCCP) .......................................................................................................................... +3.3V ±5% Operating Range(1) (T) ..................................................................................................................... 0oC to +85oC NOTE: (1) Lower limit of specification is ambient temperature and upper limit is case temperature. ESD Ratings Proper ESD procedures should be used when handling this product. The VSC830 is rated to the following ESD voltages based on the human body model: 1. All pins are rated at or above 1500V. Page 6 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Cama