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MOSEL VITELIC
V29C51001T/V29C51001B 1 MEGABIT (131,072 x 8 BIT) 5 VOLT CMOS FLASH MEMORY
Description
PRELIMINARY
Features
s s s s s s 128Kx8-bit Organization Address Access Time: 45, 70, 90 ns Single 5V ± 10% Power Supply Sector Erase Mode Operation 8KB Boot Block (lockable) 512 bytes per Sector, 256 Sectors – Sector-Erase Cycle Time: 10ms (Max) – Byte-Program Cycle Time: 20µs (Max) Minimum 10,000 Erase-Program Cycles Low power dissipation – Active Read Current: 20mA (Typ) – Active Program Current: 30mA (Typ) – Standby Current: 100µA (Max) Hardware Data Protection Low VCC Program Inhibit Below 2.5V Self-timed program/erase operations with endof-cycle detection – DATA Polling – Toggle Bit CMOS and TTL Interface Available in two versions – V29C51001T (Top Boot Block) – V29C51001B (Bottom Boot Block) Packages: – 32-pin Plastic DIP – 32-pin TSOP-I – 32-pin PLCC
s s
s s s
s s
The V29C51001T/V29C51001B is a high speed 131,072 x 8 bit CMOS flash memory. Programming or erasing the device is done with a single 5 Volt power supply. The device has separate chip enable CE, program enable WE, and output enable OE controls to eliminate bus contention. The V29C51001T/V29C51001B offers a combination of features: Boot Block with Sector Erase Mode. The end of program/erase cycle is detected by DATA Polling of I/O7 or by the Toggle Bit I/O6. The V29C51001T/V29C51001B features a sector erase operation which allows each sector to be erased and reprogrammed without affecting data stored in other sectors. The device also supports full chip erase. Boot block architecture enables the device to boot from a protected sector loaded either at the top (V29C51001T) or the bottom (V29C51001B) sector. All inputs and outputs are CMOS and TTL compatible. The V29C51001T/V29C51001B is ideal for applications that require updatable code and data storage.
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Device Usage Chart
Operating Temperature Range 0°C to 70°C Package Outline P • T • J • 45 • Access Time (ns) 70 • 90 • Power Temperature Mark Blank
Std.
•
V29C51001T/V29C51001B Rev. 0.8 October 2000
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MOSEL VITELIC
V 29 C 51 001 T –
V29C51001T/V29C51001B
OPERATING VOLTAGE 51: 5V 31: 3V
DEVICE 45: 45ns 70: 70ns 90: 90ns
SPEED P = PDIP T = TSOP-I J = PLCC
PKG. POWER TEMP. BLANK (0°C TO 70°C)
BOOT BLOCK LOCATION T: TOP B: BOTTOM
BLANK (STANDARD)
51001-01
Pin Configurations
N/C A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 32-Pin PDIP 26 Top View 25 24 23 22 21 20 19 18 17
51001-02
Pin Names
VCC WE NC A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
A0–A16 I/O0–I/O7 CE OE WE VCC GND NC
Address Inputs Data Input/Output Chip Enable Output Enable Program Enable 5V ± 10% Power Supply Ground No Connect
VCC
WE
A12
A15
A16
NC
NC
4
3
2
1 32 31 30 29 28 27 26 25 24 23 22 21
A7 A6 A5 A4 A3 A2 A1 A0 I/O0
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
A14 A13 A8 A9 A11 OE A10 CE I/O7
32 Pin PLCC Top View
A11 A9 A8 A13 A14 NC WE VCC N/C A16 A15 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32-Pin TSOP I Standard Pinout Top View
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
51001-04
OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3
I/O1
I/O2
I/O3
I/O4
I/O5
GND
I/O6
51001-03
V29C51001T/V29C51001B Rev. 0.8 October 2000
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MOSEL VITELIC
Functional Block Diagram
V29C51001T/V29C51001B
X-Decoder
1,048,576 Bit Memory Cell Array
A0–A16
Address buffer & latches
Y-Decoder
CE OE WE
Control Logic
I/O Buffer & Data Latches
I/O0–I/O7
51001-05
Capacitance (1,2)
Symbol
CIN COUT CIN2
Parameter
Input Capacitance Output Capacitance Control Pin Capacitance
Test mSetup
VIN = 0 VOUT = 0 VIN = 0
Typ.
6 8 8
Max.
8 12 10
Units
pF pF pF
NOTE: 1. Capacitance is sampled and not 100% tested. 2. TA = 25°C, VCC = 5V ± 10%, f = 1 MHz.
Latch Up Characteristics(1)
Parameter
Input Voltage with Respect to GND on A9, OE Input Voltage with Respect to GND on I/O, address or control pins VCC Current NOTE: 1. Includes all pins except VCC. Test conditions: VCC = 5V, one pin at a time.
Min.
-1 -1 -100
Max.
+13 VCC + 1 +100
Unit
V V mA
AC Test Load
+5.0 V IN3064 or Equivalent Device Under Test IN3064 or Equivalent CL = 100 pF 6.2 kΩ IN3064 or Equivalent IN3064 or Equivalent
51001-06
2.7 kΩ
V29C51001T/V29C51001B Rev. 0.8 October 2000
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Absolute Maximum Ratings(1)
Symbol
VIN VIN VCC TSTG TOPR IOUT
V29C51001T/V29C51001B
Parameter
Input Voltage (input or I/O pins) Input Voltage (A9 pin, OE) Power Supply Voltage Storage Temperature (Plastic) Operating Temperature Short Circuit Current(2)
Commercial
-2 to +7 -2 to +13 -0.5 to +5.5 -65 to +125 0 to +70 200 (Max.)
Unit
V V V °C °C mA
NOTE: 1. Stress greater than those listed unders “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. No more than one output maybe shorted at a time and not exceeding one second long.
DC Electrical Characteristics
(over the commercial operating range)
Parameter Name
VIL VIH IIL IOL VOL VOH ICC1
Parameter
Input LOW Voltage Input HIGH Voltage Input Leakage Current Output Leakage Current Output LOW Voltage Output HIGH Voltage Read Current
Test Conditions
VCC = VCC Min. VCC = VCC Max. VIN = GND to VCC, VCC = VCC Max. VOUT = GND to VCC, VCC = VCC Max. VCC = VCC Min., IOL = 2.1mA VCC = VCC Min, IOH = -400µA CE = OE = VIL, WE = VIH, all I/Os open, Address input = VIL/VIH, at f = 1/tRC Min., VCC = VCC Max. CE = WE = VIL, OE = VIH, VCC = VCC Max. CE = OE = WE = VIH, VCC = VCC Max. CE = OE = WE = VCC – 0.3V, VCC = VCC Max. CE = OE = VIL, WE = VIH CE = OE = VIL, WE = VIH, A9 = VH Max.
Min.
— 2 — — — 2.4 —
Max.
0.8 — ±1 ±1 0.4 — 40
Unit
V V µA µA V V mA
ICC2 ISB ISB1 VH IH
Program Current TTL Standby Current CMOS Standby Current Device ID Voltage for A9 Device ID Current for A9
— — — 11.5 —
50 2 150 12.5 50
mA mA µA V µA
V29C51001T/V29C51001B Rev. 0.8 October 2000
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AC Electrical Characteristics
(over all temperature ranges) Read Cycle
Parameter Name
tRC tAA tCE tOE tCLZ tOLZ tDF tOH
V29C51001T/V29C51001B
-45 Parameter
Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time CE Low to Output Active OE Low to Output Active Output Enable or Chip Disable to Output in High Z Output Hold from Address Change
-70 Max.
— 45 45 25 — — 15
-90 Max.
— 70 70 35 — — 20
Min.
45 — — — 0 0 0
Min.
70 — — — 0 0 0
Min.
90 — — — 0 0 0
Max.
— 90 90 45 — — 30
Unit
ns ns ns ns ns ns ns
0
—
0
—
0
—
ns
Program (Erase/Program) Cycle
Parameter Name
tWC tAS tAH tCS tCH tOES tOEH tWP tWPH tDS tDH tWHWH1 tWHWH2 tWHWH3
-45 Parameter
Program Cycle Time Address Setup Time Address Hold Time CE Setup Time CE Hold Time OE Setup Time OE High Hold Time WE Pulse Width WE Pulse Width High Data Setup Time Data Hold Time Programming Cycle Sector Erase Cycle Chip Erase Cycle
-70
-90
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
45 0 35 0 0 0 0 25 20 20 0 — — — — — — — — — — — — — — — — 2 — — — — — — — — — — — 20 10 — 70 0 45 0 0 0 0 35 35 25 0 — — — — — — — — — — — — — — — — 2 — — — — — — — — — — — 20 10 — 90 0 45 0 0 0 0 45 38 30 0 — — — — — — — — — — — — — — — — 2 — — — — — — — — — — — 20 10 — ns ns ns ns ns ns ns ns ns ns ns µs ms sec
V29C51001T/V29C51001B Rev. 0.8 October 2000
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MOSEL VITELIC
Waveforms of Read Cycle
tRC ADDRESS tAA CE tCE tOE OE tOLZ WE tCLZ I/O HIGH-Z tOH VALID DATA OUT tAA
V29C51001T/V29C51001B
tDF
VALID DATA OUT
HIGH-Z
51001-07
Waveforms of WE Controlled-Program Cycle
3rd bus cycle tWC tAS ADDRESS 5555H tCH CE PA tAH PA(2) tRC
OE tOES WE tCS tWPH tDS tDH I/O A0H PD(3) I/O7(1) DOUT tOH
51001-08
tWP
tWHWH1
tDF tOE
NOTES: 1. I/O7: The output is the complement of the data written to the device. 2. PA: The address of the memory location to be programmed. 3. PD: The data at the byte address to be programmed.
V29C51001T/V29C51001B Rev. 0.8 October 2000
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MOSEL VITELIC
Waveforms of CE Controlled-Program Cycle
tWC ADDRESS 5555H PA tAS tAH WE PA(1)
V29C51001T/V29C51001B
tRC
OE tWP CE tOES tWPH tDS tDH I/O A0H PD(2) I/O7 DOUT tOH
51001-09
tWHWH1
tDF tOE
Waveforms of Erase Cycle(1)
tWC ADDRESS 5555H tAS 2AAAH 5555H tAH CE 5555H 2AAAH SA
OE tWP WE tCS tDS tDH I/O AAH 55H 80H AAH 55H tWPH 10H for Chip Erase 30H
51001-10
NOTES: 1. PA: The address of the memory location to be programmed. 2. PD: The data at the byte address to be programmed. 3. SA: The sector address for Sector Erase. Address = don’t care for Chip Erase.
V29C51001T/V29C51001B Rev. 0.8 October 2000
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MOSEL VITELIC
Waveforms of DATA Polling Cycle
tCH CE tOE OE tOEH WE tCE tWHWH1 I/O7 I/O7 I/O7
V29C51001T/V29C51001B
tDF
tOH HIGH-Z
VALID DATA OUT
I/O0-I/O6
I/O0-I/O6
INVALID
VALID DATA OUT
HIGH-Z
51001-11
Waveforms of Toggle Bit Cycle
CE tOEH WE
OE
I/O6
51001-12
V29C51001T/V29C51001B Rev. 0.8 October 2000
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Functional Description
The V29C51001T/V29C51001B consists of 256 equally-sized sectors of 512 bytes each. The 8 KB lockable Boot Block is intended for storage of the system BIOS boot code. The boot code is the first piece of code executed each time the system is powered on or rebooted. The V29C51001 is available in two versions: the V29C51001T with the Boot Block address starting from 1E000H to 1FFFFH, and the V29C51001B with the Boot Block address starting from 00000H to 1FFFFH.
V29C51001T 8KB Boot Block 512 512 • •
