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Elpida Memory
Elpida Memory

UPD4564163 Datasheet

(UPD4564841/441/163) 64M-bit SDRAM / 4-Bank


UPD4564163 Datasheet Preview


DATA SHEET
MOS INTEGRATED CIRCUIT
µPD4564441, 4564841, 4564163
64M-bit Synchronous DRAM
4-bank, LVTTL
Description
The µPD4564441, 4564841, 4564163 are high-speed 67,108,864-bit synchronous dynamic random-access
memories, organized as 4,194,304 × 4 × 4, 2,097,152 × 8 × 4, 1,048,576 ×16 × 4 (word × bit × bank), respectively.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).
These products are packaged in 54-pin TSOP (II).
Features
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
Pulsed interface
Possible to assert random column address in every cycle
Quad internal banks controlled by A12 and A13 (Bank Select)
Byte control (×16) by LDQM and UDQM
Programmable Wrap sequence (Sequential / Interleave)
Programmable burst length (1, 2, 4, 8 and full page)
Programmable /CAS latency (2 and 3)
Automatic precharge and controlled precharge
CBR (auto) refresh and self refresh
• ×4, ×8, ×16 organization
Single 3.3 V ± 0.3 V power supply
LVTTL compatible inputs and outputs
4,096 refresh cycles / 64 ms
Burst termination by Burst stop command and Precharge command
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
Document No. E0149N10 (Ver.1.0)
(Previous No. M12621EJCV0DS00)
Date Published August 2001 (K)
Printed in Japan
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
Page 1

Ordering Information
Part number
µPD4564441G5-A80-9JF
µPD4564441G5-A10-9JF
µPD4564441G5-A10B-9JF
µPD4564841G5-A80-9JF
µPD4564841G5-A10-9JF
µPD4564841G5-A10B-9JF
µPD4564163G5-A80-9JF
µPD4564163G5-A10-9JF
µPD4564163G5-A10B-9JF
µPD4564441, 4564841, 4564163
Organization
(word × bit × bank)
4M × 4 × 4
2M × 8 × 4
1M × 16 × 4
Clock frequency
MHz (MAX.)
125
100
100
125
100
100
125
100
100
Package
54-pin Plastic TSOP (II)
(10.16mm (400))
2 Data Sheet E0149N10
Page 2

µPD4564441, 4564841, 4564163
Part Number
[ x4, x8 ]
µPD4564841G5 - A80
NEC Memory
Synchronous DRAM
Memory density
64 : 64M bits
Organization
4 : x4
8 : x8
Minimum cycle time
80 : 8 ns (125 MHz)
10 : 10 ns (100 MHz)
10B : 10 ns (100 MHz)
Number of banks
4 : 4 banks
Interface
1 : LVTTL
[ x16 ]
163
Low voltage
A : 3.3 ± 0.3 V
Package
G5 : TSOP (II)
Organization
16 : x16
Number of banks
and Interface
3 : 4 banks, LVTTL
Data Sheet E0149N10
3
Page 3
Part Number UPD4564163
Manufactur Elpida Memory
Description (UPD4564841/441/163) 64M-bit SDRAM / 4-Bank
Total Page 30 Pages
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