HIGH-EFFICIENCY PREDICTIVE SYNCHRONOUS BUCK DRIVER

www.DataSheet4U.com UCC27223 SLUS558 − DECEMBER 2003 HIGH EFFICIENCY PREDICTIVE SYNCHRONOUS BUCK DRIVER WITH ENABLE FEATURES D Maximizes Efficiency by Minimizing D D D D D D D D Body-Diode Conduction and Reverse Recovery Losses Transparent Synchronous Buck Gate Drive Operation From the Single Ended PWM Input Signal 12-V or 5-V Input Operation 3.3-V Input Operation With Availability of 12-V Bus Bias High-Side and Low-Side ±3-A Dual Drivers On-Board 6.5-V Gate Drive Regulator ±3-A TrueDrive Gate Drives for High Current Delivery at MOSFET Miller Thresholds Automatically Adjusts for Changing Operating Conditions Thermally Enhanced 14-Pin PowerPAD HTSSOP Package Minimizes Board Area and Junction Temperature Rise APPLICATIONS D Multiphase Converters in Combination With D the TPS40090 Non-Isolated 3.3-V, 5-V and 12-V Input dc-to-dc Converters for Processor Power, General Computer, Telecom and Datacom Applications DESCRIPTION The UCC27223 is a high-speed synchronous buck drivers for today’s high-efficiency, lower-output voltage designs. Using Predictive Gate Drivet (PGD) control technology, these drivers reduce diode conduction and reverse recovery losses in the synchronous rectifier MOSFET(s). The UCC27223 includes an enable pin that controls the operation of both outputs. A logic latch is also included to keep both outputs low until the first PWM input pulse comes in. The RDS(on) of the SR pull-down sourcing device is also minimized for higher frequency operations. This closed loop feedback system detects body-diode conduction, and adjusts deadtime delays to minimize the conduction time interval. This virtually eliminates body-diode conduction while adjusting for temperature, load- dependent delays, and for different MOSFETs. Precise gate timing at the nanosecond level reduces the reverse recovery time of the synchronous rectifier MOSFET body-diode, reducing reverse recovery losses seen in the main (high-side) MOSFET. The lower junction temperature in the low-side MOSFET increases product reliability. Since the power dissipation is minimized, a higher switching frequency can also be used, allowing for smaller component sizes. The UCC27223 is offered in the thermally enhanced 14-pin PowerPADt package with 2°C/W θjc. FUNCTIONAL APPLICATION DIAGRAM VIN UCC27223 7 PWMIN 6,8 GND 3 2 VDD ENBL SW 11,12 G1 13 IN VHI 14 VOUT 4,5 VLO G2 9,10 GNDOUT GNDIN Note: 12-V input system shown. For 5-V input only systems, see Figure 6. Predictive Gate Drivet and PowerPADt are trademarks of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2003, Texas Instruments Incorporated www.ti.com 1 UCC27223 SLUS558 − DECEMBER 2003 PWP PACKAGE (TOP VIEW) N/C ENBL VDD VLO PVLO AGND IN 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VHI G1 SW SWS G2S G2 PGND N/C − No internal connection AVAILABLE OPTIONS PACKAGED DEVICES TA −40_C to 105_C PWM INPUT (IN) NON-INVERTING PowerPADt HTSSOP−14 (PWP) UCC27223PWP {The PWP package is available taped and reeled. Add R suffix to device type (e.g. UCC27223PWPR) to order quantities of 2,000 devices per reel and 90 units per tube. absolute maximum ratings over operating free-air temperature (unless otherwise noted)†} Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 to 20 V Input voltage, VHI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V SW, SWS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V Supply current, IDD, including gate drive current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 mA Sink current (peak) pulsed, G1/G2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 A Source current (peak) pulsed, G1/G2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −4.0 A Analog inputs, IN, ENBL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −3.0 V to VDD + 0.3 V, not to exceed 15 V Power Dissipation at TA = 25°C (PWP package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 W Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 115°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Lead temperature soldering 1.6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 300°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ All voltages are with respect to AGND and PGND. Currents are positive into, negative out of the specified terminal. 2 www.ti.com UCC27223 SLUS558 − DECEMBER 2003 ELECTRICAL CHARACTERISTICS VDD = 12-V, 1-µF capacitor from VDD to GND, 1-µF capacitor from VHI to SW, 0.1-µF and 2.2-µF capacitor from PVLO to PGND, PVLO tied to VLO, TA = −40_C to 105_C for the UCC27223, TA = TJ (unless otherwise noted) VLO regulator PARAMETER VDD = 12 V, VDD = 20 V, VDD = 10 V, VDD = 12 V to 20 V IVLO = 0 mA to 100 mA VDD = 8.5 V VLO = 6.175 V, IVLO = 100 mA 7.1 TEST CONDITIONS IVLO = 0 mA IVLO = 0 mA IVLO = 100 mA MIN 6.2 6.2 6.1 TYP 6.5 6.5 6.5 2 15 220 7.8 8.5 MAX 6.8 6.8 6.9 10 40 mV mA V V UNIT Regulator output voltage Line Regulation Load Regulation Short-circuit current(1) Dropout voltage, (VDD at 5% VLO drop) undervoltage lockout PARAMETER Start threshold voltage Minimum operating voltage after start Hysteresis TEST CONDITIONS Measured at VLO MIN 3.30 3.15 0.07 TYP 3.82 3.70 0.12 MAX 4.40 4.15 0.20 V UNIT bias currents PARAMETER VLO bias current at VLO (ON), 5 V applications only VDD bias current VLO = 4.5 V, VDD = 8.5 V fIN = 500 kHz, No load on G1/G2 TEST CONDITIONS VDD = no connect MIN 3.6 5.5 8 TYP 4.7 7.1 16 MAX 5.8 8.5 25 mA UNIT input command (IN) PARAMETER High-level input voltage Low-level input voltage Input bias current TEST CONDITIONS 10 V < VDD < 20 V 10 V < VDD < 20 V VDD = 15 V MIN 3.3 2.2 TYP 3.6 2.5 MAX 3.9 2.8 1 V µA UNIT input (SWS) PARAMETER High-level input threshold voltage TEST CONDITIONS fIN = 500 kHz, G2S = 0.0 V fIN = 500 kHz, G2S = 0.0 V fIN = 500 kHz, SWS = 0.0 V tON, G2 maximum, tON, G2 minimum, tON, G1 minimum MIN 1.4 0.7 −100 −0.9 TYP 2.0 1.0 −300 −1.2 MAX 2.6 V 1.3 −500 −1.5 mV mA UNIT Low-level input threshold voltage Input bias current input (G2S) PARAMETER High-level input voltage Low-level input voltage Input bias current NOTE 1: Ensured by design. Not production tested. TEST CONDITIONS fIN = 500 kHz, SWS = 0.0 V fIN = 500 kHz, SWS = 0.0 V G2S = 0 V tON, G2 maximum, tON, G2 minimum, MIN 1.4 0.7 −370 TYP 2.0 1.0 −470 MAX 2.6 V 1.3 −570 µA UNIT www.ti.com 3 UCC27223 SLUS558 − DECEMBER 2003 ELECTRICAL CHARACTERISTICS VDD = 12-V, 1-µF capacitor from VDD to GND, 1-µF capacitor from VHI to SW, 0.1-µF and 2.2-µF capacitor from PVLO to PGND, PVLO tied to VLO, TA = −40_C to 105_C for the UCC27223, TA = TJ (unless otherwise noted) enable (ENBL) PARAMETER VIN_H, high-level input voltage VIN_L, low-level input voltage Hysteresis RENBL, enable impedance tD3, propagation delay time(5) tD4, propagation delay time(5) tr, Rise time tf, Fall time VLO = PVLO = 8.5 V VLO = PVLO = 8.5 V VDD = 14 V, ENBL = GND 75 LO to HI transition HI to LO transition TEST CONDITION MIN 2.25 1.55 TYP 2.45 1.70 1.1 112 TBD TBD 2.5 2.5 ms ns 150 kΩ MAX 2.85 1.90 V UNITS G1 main output PARAMETER Sink resistance Source resistance(2) Source current(1)(2) Sink current(1)(2) Rise time Fall time SW = 0 V, SW = 0 V, SW = 0 V, SW = 0 V, TEST CONDITIONS VHI = 6 V, VHI = 6 V, VHI = 6 V, VHI = 6 V, IN = 0 V, IN = 6.5 V, IN = 6.5 V, IN = 0 V, G1 = 0.5 V G1 = 5.5 V G1 = 3.0 V G1 = 3.0 V VDD = 20 V VDD = 20 V MIN 0.5 10 −3 3 TYP 0.9 25 −3.3 3.3 17 17 25 25 ns A MAX 1.5 45 UNIT Ω C = 2.2 nF from G1 to SW, C = 2.2 nF from G1 to SW, G2 SR output PARAMETER Sink resistance(2) Source resistance(2) Source current(1)(2) Sink current(1)(2) Rise time(2) Fall time TEST CONDITIONS PVLO = 6.5 V, PVLO = 6.5 V, PVLO = 6.5 V, PVLO = 6.5 V, IN = 6.5 V, IN = 0 V, IN = 0 V IN = 6.5 V G1 = 0.25 V G2 = 6.0 V G2 = 3.25 V G2 = 3.25 V MIN 0.5 10 3 −3 TYP 1.6 20 3.3 3.3 17 20 25 35 ns A MAX 4.0 35 UNIT Ω C = 2.2 nF from G2 to PGND VDD = 20 V C = 2.2 nF from G2 to PGND VDD = 20 V deadtime delay PARAMETER tOFF, G2, IN to G2 falling tOFF, G1, IN to G1 falling Delay Step Resolution tON, G1 minimum tON, G1 maximum tON, G2 minimum tON, G2 maximum TEST CONDITIONS MIN 40 55 4.0 TYP 80 80 4.5 −17 49 −15 54 MAX 125 110 5.2 ns UNIT NOTE 1: Ensured by design. Not production tested. 2: The pullup / pulldown circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance is the RDS(ON) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. 4 www.ti.com UCC27223 SLUS558 − DECEMBER 2003 tOFF,G1 3.25 V UCC27223 IN tOFF,G2 tOn,G1 tOn