UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5
Current Mode PWM Controller
FEATURES • • • • • • • • • • • Optimized For Off-line And DC To DC Converters Low Start Up Current (<1mA) Automatic Feed Forward Compensation Pulse-by-pulse Current Limiting Enhanced Load Response Characteristics Under-voltage Lockout With Hysteresis Double Pulse Suppression High Current Totem Pole Output Internally Trimmed Bandgap Reference 500khz Operation Low RO Error Amp DESCRIPTION The UC1842/3/4/5 family of control ICs provides the necessary features to implement off-line or DC to DC fixed frequency current mode control schemes with a minimal external parts count. Internally implemented circuits include under-voltage lockout featuring start up current less than 1mA, a precision reference trimmed for accuracy at the error amp input, logic to insure latched operation, a PWM comparator which also provides current limit control, and a totem pole output stage designed to source or sink high peak current. The output stage, suitable for driving N Channel MOSFETs, is low in the off state. Differences between members of this family are the under-voltage lockout thresholds and maximum duty cycle ranges. The UC1842 and UC1844 have UVLO thresholds of 16V (on) and 10V (off), ideally suited to off-line applications. The corresponding thresholds for the UC1843 and UC1845 are 8.4V and 7.6V. The UC1842 and UC1843 can operate to duty cycles approaching 100%. A range of zero to 50% is obtained by the UC1844 and UC1845 by the addition of an internal toggle flip flop which blanks the output off every other clock cycle.
BLOCK DIAGRAM
Note 1: A/B Note 2:
A = DIL-8 Pin Number. B = SO-14 and CFP-14 Pin Number. Toggle flip flop used only in 1844 and 1845.
SLUS223A - APRIL 1997 - REVISED MAY 2002
ABSOLUTE MAXIMUM RATINGS(Note 1)
Supply Voltage (Low Impedance Source) . . . . . . . . . . . . . . 30V Supply Voltage (ICC < 30mA) . . . . . . . . . . . . . . . . . Self Limiting Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1A Output Energy (Capacitive Load) . . . . . . . . . . . . . . . . . . . . 5 µJ Analog Inputs (Pins 2, 3). . . . . . . . . . . . . . . . . . . -0.3V to +6.3V Error Amp Output Sink Current . . . . . . . . . . . . . . . . . . . . 10 mA Power Dissipation at TA ≤ 25°C (DIL−8) . . . . . . . . . . . . . . . . . 1 W Power Dissipation at TA ≤ 25°C (SOIC-14) . . . . . . . . . 725 mW Storage Temperature Range . . . . . . . . . . . . . . -65°C to +150°C Junction Temperature Range . . . . . . . . . . . . . -55°C to +150°C Lead Temperature (soldering, 10 seconds) . . . . . . . . . . . 300°C Note 1: All voltages are with respect to Pin 5. All currents are positive into the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages.
UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5
CONNECTION DIAGRAMS
DIL-8, SOIC-8 (TOP VIEW) N or J Package, D8 Package PLCC-20 (TOP VIEW) Q Package
PACKAGE PIN FUNCTION FUNCTION PIN 1 N/C COMP 2 N/C 3 N/C 4 VFB 5 N/C 6 ISENSE 7 N/C 8 N/C 9 RT/CT 10 N/C 11 PWR GND 12 GROUND 13 N/C 14 OUTPUT 15 N/C 16 VC 17 VCC 18 N/C 19 VREF 20
SOIC-14, CFP-14. (TOP VIEW) D or W Package
DISSIPATION RATING TABLE
Package W TA ≤ 25°C Power Rating 700 mW Derating Factor Above TA ≤ 25°C 5.5 mW/°C TA ≤ 70°C Power Rating 452 mW TA ≤ 85°C Power Rating 370 mW TA ≤ 125°C Power Rating 150 mW
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UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5
ELECTRICAL CHARACTERISTICS:
Unless otherwise stated, these specifications apply for -55°C ≤ TA ≤ 125°C for the UC184X; -40°C ≤ TA ≤ 85°C for the UC284X; 0°C ≤ TA ≤ 70°C for the 384X; VCC = 15V (Note 5); RT = 10k; CT = 3.3nF, TA=TJ. TEST CONDITIONS UC1842/3/4/5 UC2842/3/4/5 MIN Reference Section Output Voltage Line Regulation Load Regulation Temp. Stability Total Output Variation Output Noise Voltage Long Term Stability Output Short Circuit Oscillator Section Initial Accuracy Voltage Stability Temp. Stability Amplitude Error Amp Section Input Voltage Input Bias Current AVOL Unity Gain Bandwidth PSRR Output Sink Current Output Source Current VOUT High VOUT Low Current Sense Section Gain Maximum Input Signal PSRR Input Bias Current Delay to Output Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: VPIN 3 = 0 to 2V (Note 2) (Notes 3 and 4) VPIN 1 = 5V (Note 3) 12 ≤ VCC ≤ 25V (Note 3) (Note 2) 2.85 0.9 3 1 70 -2 150 -10 300 3.15 1.1 2.85 0.9 3 1 70 -2 150 -10 300 3.15 1.1 V/V V dB µA ns 2 ≤ VO ≤ 4V (Note 2) TJ = 25°C 12 ≤ VCC ≤ 25V VPIN 2 = 2.7V, VPIN 1 = 1.1V VPIN 2 = 2.3V, VPIN 1 = 5V VPIN 2 = 2.3V, RL = 15k to ground VPIN 2 = 2.7V, RL = 15k to Pin 8 65 0.7 60 2 -0.5 5 VPIN 1 = 2.5V 2.45 2.50 -0.3 90 1 70 6 -0.8 6 0.7 1.1 2.55 -1 65 0.7 60 2 -0.5 5 2.42 2.50 -0.3 90 1 70 6 -0.8 6 0.7 1.1 2.58 -2 V µA dB MHz dB mA mA V V TJ = 25°C (Note 6) 12 ≤ VCC ≤ 25V TMIN ≤ TA ≤ TMAX (Note 2) VPIN 4 peak to peak (Note 2) 47 52 0.2 5 1.7 57 1 47 52 0.2 5 1.7 57 1 kHz % % V TJ = 25°C, IO = 1mA 12 ≤ VIN ≤ 25V 1 ≤ I0 ≤ 20mA (Note 2) (Note 7) Line, Load, Temp. (Note 2) 10Hz ≤ f ≤ 10kHz, TJ = 25°C (Note2) TA = 125°C, 1000Hrs. (Note 2) -30 4.9 50 5 -100 25 -180 -30 4.95 5.00 6 6 0.2 5.05 20 25 0.4 5.1 4.82 50 5 -100 25 -180 4.90 5.00 6 6 0.2 5.10 20 25 0.4 5.18 V mV mV mV/°C V µV mV mA TYP MAX UC3842/3/4/5 MIN TYP MAX UNITS
PARAMETER
These parameters, although guaranteed, are not 100% tested in production. Parameter measured at trip point of latch with VPIN 2 = 0. Gain defined as ∆ VPIN 1 A= , 0 ≤ VPIN 3 ≤ 0.8V ∆ VPIN 3 Adjust VCC above the start threshold before setting at 15V. Output frequency equals oscillator frequency for the UC1842 and UC1843. Output frequency is one half oscillator frequency for the UC1844 and UC1845. Temperature stability, sometimes referred to as average temperature coefficient, is described by the equation: V (max ) − VREF (min) Temp Stability = REF TJ (max ) − TJ (min) VREF (max) and VREF (min) are the maximum and minimum reference voltages measured over the appropriate temperature range. Note that the extremes in voltage do not necessarily occur at the extremes in temperature.
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UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5
ELECTRICAL CHARACTERISTICS:
Unless otherwise stated, these specifications apply for −55°C ≤ TA ≤ 125°C for the UC184X; −40°C ≤ TA ≤ 85°C for the UC284X; 0°C ≤ TA ≤ 70°C for the 384X; VCC = 15V (Note 5); RT = 10k; CT = 3.3nF, TA=TJ. TEST CONDITION UC1842/3/4/5 UC2842/3/4/5 MIN Output Section Output Low Level Output High Level Rise Time Fall Time Under-voltage Lockout Section Start Threshold Min. Operating Voltage After Turn On PWM Section Maximum Duty Cycle Minimum Duty Cycle Total Standby Current Start-Up Current Operating Supply Current VPIN 2 = VPIN 3 = 0V 0.5 11 1 17 30 0.5 11 34 1 17 mA mA V X842/3 X844/5 95 46 97 48 100 50 0 95 47 97 48 100 50 0 % % % X842/4 X843/5 X842/4 X843/5 15 7.8 9 7.0 16 8.4 10 7.6 17 9.0 11 8.2 14.5 7.8 8.5 7.0 16 8.4 10 7.6 17.5 9.0 11.5 8.2 V V V V ISINK = 20mA ISINK = 200mA ISOURCE = 20mA ISOURCE = 200mA TJ = 25°C, CL = 1nF (Note 2) TJ = 25°C, CL = 1nF (Note 2) 13 12 0.1 1.5 13.5 13.5 50 50 150 150 0.4 2.2 13 12 0.1 1.5 13.5 13.5 50 50 150 150 0.4 2.2 V V V V ns ns TYP MAX UC3842/3/4/5 MIN TYP MAX UNITS
PARAMETER
VCC Zener Voltage ICC = 25mA 30 34 Note 2: These parameters, although guaranteed, are not 100% tested in production. Note 3: Parameter measured at trip point of latch with VPIN 2 = 0 . ∆ VPIN 1 Note 4: Gain defined as: A = ; 0 ≤ VPIN 3 ≤ 0.8V . ∆ VPIN 3 Note 5: Adjust VCC above the start threshold before setting at 15V. Note 6: Output frequency equals oscillator frequency for the UC1842 and UC1843. Output frequency is one half oscillator frequency for the UC1844 and UC1845.
ERROR AMP CONFIGURATION
Error Amp can Source or Sink up to 0.5mA 4
UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5 UNDER-VOLTAGE LOCKOUT
During under-voltage lock-out, the output driver is biased to sink minor amounts of current. Pin 6 should be shunted to ground with a bleeder resistor to prevent
activating the power switch with extraneous leakage currents.
CURRENT SENSE CIRCUIT
Peak Current (IS) is Determined By The Formula 1.0V ISMAX ′ RS
A small RC filter may be required to suppress switch transients.
OSCILLATOR SECTION
5
UC1842/3/4/5 UC2842/3/4/5 OUTPUT SATURATION CHARACTERISTICS ERROR AMPLIFIER OPEN-LOOP FREQUENCY RESPONSE
OPEN-LOOP LABORATORY FIXTURE
High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to pin 5 in a
single point ground. The transistor and 5k potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin 3.
SHUT DOWN TECHNIQUES
Shutdown of the UC1842 can be accomplished by two methods; either raise pin 3 above 1V or pull pin 1 below a voltage two diode drops above ground. Either method causes the output of the PWM comparator to be high (refer to block diagram). The PWM latch is reset dominant so that the output will remain low until the next 6
clock cycle after the shutdown condition at pin 1 and/or 3 is removed. In one example, an externally latched shutdown may be accomplished by adding an SCR which will be reset by cycling VCC below the lower UVLO threshold. At this point the reference turns off, allowing the SCR to reset.
UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5 OFFLINE FLYBACK REGULATOR
Power Supply Specifications 1. Input Voltages 2. Line Isolation 3. Switching Frequency 5VAC to 130VA (50 Hz/60Hz) 3750V 40kHz
5. Output Voltage: A. +5V, ±5%; 1A to 4A load Ripple voltage: 50mV P-P Max B. +12V, ±3%; 0.1A to 0.3A load Ripple voltage: 100mV P-P Max C. -12V ,±3%; 0.1A to 0.3A load Ripple voltage: 100mV P-P Max
4. Efficiency at Full Load 70%
SLOPE COMPENSATION
A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope compensation for converters requ
