Low-Power FM Transmitter

U3550BM Low-Power FM Transmitter / Synthesizer System 26 to 50 MHz Description The U3550BM is a radio-frequency IC for analog cordless telephone applications in the 26/50-MHz band (CTO standard). The IC performs full duplex communication. The transmitting and receiving frequency depends on whether the IC is used in the handset or in the base station. The U3550BM’s frequency converter consists of an FM transmitter with switchable output power and receiver Mixer 1 in the same unit. A two-wire bus interface can be used for frequency control as well as for switching the transmitter’s power amplifier and the receiver. Fine frequency adjustment of the reference crystal oscillator is programmable. The receive part is designed for a double-conversion architecture. The incoming radio-frequency signal will be filtered and amplified before reaching the first mixer. At this stage, the RF signal will be converted down to the first intermediate frequency (10.7 MHz) by using a local adjustable oscillator (VCO3). The frequency of this oscillator is controlled by the PLL. The transmitter part contains two PLL-controlled VCOs. The frequency modulation is accomplished by superposing the incoming audio signal on the first PLL control voltage. In this system, the frequency is a product of mixing VCO1 with local oscillator (VCO3). The FMmodulated carrier is amplified by external power amplifier before entering the output filter and the antenna connector. Features D All PLLs and most of the oscillators are integrated D All functions and channel selection controllable by D D D D Application Korea, Taiwan, New Zealand, China) serial bus D Narrowband voice and data transmitting / receiving Receiver Mixer 1 with integrated image rejection systems Up to 25 channels selectable depending on CT0 standard www.DataSheet4U.com Integrated oscillator circuit with external crystal (11.15 MHz) Programmable carrier-modulation frequency VBAT DELVB DELGND MIXO Mixer 1 + 45 – 45 sin LOGND PCLO OSCVDD MCKA OSCGND XCK MCKO Block Diagram VCC om po ne 10.7 MHz cos 2 N Phase comparator cos D1 D2 Loop filter Phase comparator AGND VSS MODIN D CT0 (USA, France, Spain, Netherlands, Portugal, Ad ro nic C MIXIN MIXVB nt s K 20 557.5 KHz VCO 1 2 LO1 LO2 VCO 3 sin Mixer 2 + 45 – 45 VTX RFOVB RFO VCO 2 RFOGND Figure 1. Block diagram Rev. A2, 10-Sep-98 Gm bH 11.15 MHz Oscillator interface Serial BUS interface C D D3 P GREF Phase comparator LFGND MLF 13280 1 (25) Preliminary Information U3550BM Pin Description MCKO 1 D C OSCGND 2 3 4 28 VCC 27 VSS 26 MCKA 25 MODIN 24 LFGND 23 MLF 22 VBAT 21 AGND 20 VTX 19 RFOVB 18 RFO XCK 5 OSCVDD 6 DELVB 7 DELGND 8 GREF 9 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 MIXIN 10 MIXVB 11 MIXO 12 LO1 13 LO2 14 11623 17 RFOGND 16 LOGND 15 PCLO Figure 2. Pinning Order Information Extended Type Number U3550BM-AFL U3550BM-AFLG3 Ad ro nic C om po ne Package SO28 SO28 nt s Taped and reeled 2 (25) Preliminary Information Gm bH Remarks Pin 1 2 3 4 5 6 7 Function Clock output for peripherals Data input of serial bus Clock line of serial bus Oscillator ground Oscillator input (11.15 MHz) Oscillator supply input Phase correction VCO3 supply input DELGND Phase correction VCO3 ground GREF Voltage reference for internal current sources MIXIN Mixer input MIXVB Mixer-supply input MIXO Mixer output LO1 Tank elements for LO are connected to these pins LO2 PCLO Phase comparator PLL3 output LOGND VCO3 ground RFOGND RF transmit output ground RFO RF transmit output RFOVB Power-supply input of RF transmit output buffer VTX Power-supply output of RF external power amplifier AGND Analog ground VBAT Power supply of analog part MLF Modulator loop filter LFGND Modulator loop-filter ground MODIN Modulator input signal MCKA Peripheral-clock output adjustment VSS Digital ground VCC Power supply of digital part Symbol MCKO D C OSCGND XCK OSCVDD DELVB Rev. A2, 10-Sep-98 U3550BM VCO Adjustments To be able to use a wide VCO frequency range (i.e., VCO2 = 26.3 to 49.9 MHz), VCO1 and VCO2 have a rough adjust and a fine adjust to increase the frequency range given by the phase comparator. The 4 rough adjusts for VCO1 and VCO2 (3 used in VCO1) are correlated to the country setting. For each country, there are two sets of VCO rough adjust settings, one for the base and one for the handset (see tables Channel Frequencies, Dividers and Country Settings). To achieve the adaption to the various country standards, there is a fine adjust with 32 steps for VCO1 and VCO2. These fine adjusts can be set manually (for test purposes) or by the automatically mode. Theoretically, the indicator of the change (increase/ decrease when the voltage of the phase comparator is too high) is selectable. The programming value ‘1’, however, is necessary. Setting normal conditions VCO1: EAFA1 = 1, automatic fine adjust VCO1 enabled SAFA1 = 1, sign of auto fine adjustment VCO1 = 1. Setting for VCO2 is identical. For VCO3, there is no internal adjustment. Duration Adjustment of the Anti-Backlash Signals The phase comparators of the modulator- and the mixerloop have a 2-bit adjustment for the duration of the upand down pulses when the loop is locked (anti-backlash). Best results can be achieved by setting all the bits (AMOD[2:1], AMIX[2:1]) to 0. Adjustment of the Modulator Gain To fulfill all requirements of the various countries, three conversion gains of the modulator are selectable by the bits GMOD[1:0]. Clock-Output Divider Adjustment The MCKO pin is a clock output derived from the crystal oscillator. It can be used to drive a microprocessor or other remote components and thereby reduces the number of crystals required. The crystal oscillator frequency can be divided by an integer value: 1, 2, 3, 4, 6 or switched off. The divider value is adjusted by an analog level on the MCKA pin. Table 1 shows the clock-output value on MCKO for different divider values and the corresponding level required on MCKA. Crystal oscillator = 11.15 MHz. Speed-up of the Modulator Loop Filter To obtain a fast locking time for the modulator loop, there is a precharge and a speed-up mode for the external loop filter. During receive mode (VCO3 enabled, VCO1 disabled), the modulator loop filter is precharged to 1.25 V. Table 1. Clock-output values Level on MCKA Level on MCKA for VCC = 3.6 V Corresponding divider Ad ro nic C 0 to 7% VCC 0 to 0.25 X During the first 30 ms after enabling VCO1, the modulator phase comparator is in speed-up mode. In this mode, the current of the phase comparator which charges the loop filter is much larger than in normal mode. The duration of the speed-up mode depends on the number of oscillator clock cycles. 13% to 27% VCC 33% to 47% VCC 53% to 67% VCC 73% to 87% VCC 0.47 to 0.97 6 1.19 to 1.69 4 2.7875 1.91 to 2.41 3 3.716 2.63 to 3.13 2 5.575 om po ne nt s For country settings, see tables Channel Frequencies, Dividers and Country Settings. For the ranges, see tabel Electrical Characteristics (RF transmitter). Gm bH 93% to VCC 3.35 to 3.6 1 11.15 Corresponding clock on MCKO (MHz) No output 1.858 Rev. A2, 10-Sep-98 3 (25) Preliminary Information U3550BM Frequency Synthesis Loop filter 3) VCO 3 2 fLO N Phase comparator K fRef3 96 11627 D1 2) VCO 2 Loop filter Phase comparator fRef D2 VCO 1 nt s 1) Loop filter om po ne Figure 3. 1) 2) 3) Modulator loop Mixer loop Local oscillator (LO) loop Modulator Loop and Mixer Loop Dividers France Spain Netherlands Portugal USA (channels 1 to 10) USA (new channels) Taiwan New Zealand Korea D1 4 2 2 2 8 6 8 4 8 D2 8 8 8 8 8 6 8 8 8 For France, Spain, Netherlands, Portugal, Taiwan and New Zealand, fRef2 and fmod do not change when the channel changes. For USA and Korea is valid: fRef2 and fmod are varying according to the channel number. For all countries, fRef2 and fmod are identical for base set and handset. Reference Frequency Dividers for Local Oscillator K0 = 4460 K1 = 2230 K2 = 1784 K3 = 1115 K4 = 892 K5 = 446 fRef3 = 2.5 kHz fRef3 = 5 kHz fRef3 = 6.25 kHz fRef3 = 10 kHz fRef3 = 12.5 kHz fRef3 = 25 kHz 4 (25) Ad ro nic C D3 2 4 4 4 1 1 1 2 1 Preliminary Information Gm bH 11.15 MHz 2 D3 fmod Q P+ 223 Phase comparator fRef1 = 557.5 kHz fRef2 (MHz) 1.075 0.9 0.9 0.625 0.955 0.943 0.9625 0.5875 0.955 fmod (MHz) 4.3 1.8 1.8 1.25 7.64 5.66 7.70 4.70 7.64 Rev. A2, 10-Sep-98 U3550BM Modulator PLL The fractional divider has been chosen to increase reference the frequency of the modulator PLL. 557.5 kHz Local Oscillator PLL f Ref3 + fN LO mod P The circuit is remoted by an external microcontroller through the serial bus. The data is a 12-bit word: P: integer part of the fractional divider Q: fractional part of the fractional divider Q + 223 A0 – A3: address of the destination register (0 to 15) f mod –P 557.5 kHz D0 – D7: contents of register 223 kHz + 557.7kHz 2.5 The data line must be stable when the clock is high and data must be shifted serially. After a 12-clock period, the transfer to the destination register is generated (internally) by a low-to-high transition of the data line when the clock is high. The frequency step 2.5 kHz is a fraction of the reference frequency 557.5 kHz Q ³ Qx (P ) 1) ) (223–Q)P + P ) 223 223 For each comparison cycle (fRef1 = 557.5 kHz), the accumulator content is incremented by the Q value and the divider divides by the P value. When the accumulator value reaches or exceeds 223, the divider divides by the value (P + 1). Then, the accumulator holds the excess value (accumulator value – 223). After 223 cycles, the correct division is executed. om po ne nt s Microprocessor A2 A3 Gm bH Data Clock D C Figure 4. 2nd word +f Q ) 223 Serial Bus Interface 96 11787 Data (D) D0 D1 D2 A0 A1 Ad ro nic C Clock (C) 1st word 13279 Word transmission Transfer condition Figure 5. Serial bus transmission Rev. A2, 10-Sep-98 5 (25) Preliminary Information U3550BM Data 4 Clock 8 0 Address Decoder 15