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TY30N50E Datasheet

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Designer's
Data Sheet
TMOS E-FET .
Power Field Effect Transistor
N–Channel Enhancement–Mode Silicon Gate
This advanced TMOS power FET is designed to withstand high
energy in the avalanche and commutation modes. This new energy
efficient design also offers a drain–to–source diode with fast
recovery time. Designed for high voltage, high speed switching
applications in power supplies, converters, PWM motor controls,
and other inductive loads. The avalanche energy capability is
specified to eliminate the guesswork in designs where inductive
www.DataSheet4loUa.cdosmare switched and offer additional safety margin against
unexpected voltage transients.
Avalanche Energy Specified
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
®
D
Order this document
by MTY30N50E/D
MTY30N50E
Motorola Preferred Device
TMOS POWER FET
30 AMPERES
500 VOLTS
RDS(on) = 0.15 OHM
G
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Drain–Source Voltage
Drain–Gate Voltage (RGS = 1 M)
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp 10 ms)
Drain Current — Continuous @ TC = 25°C
Drain Current — Single Pulse (tp 10 µs)
Total Power Dissipation
Derate above 25°C
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 100 Vdc, VGS = 10 Vdc, Peak IL = 30 Apk, L = 10 mH, RG = 25 )
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8from case for 10 seconds
CASE 340G–02, STYLE 1
TO–264
S
Symbol
VDSS
VDGR
VGS
VGSM
ID
IDM
PD
TJ, Tstg
EAS
Value
500
500
± 20
± 40
30
80
300
2.38
– 55 to 150
3000
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
Watts
W/°C
°C
mJ
RθJC
RθJA
TL
0.42 °C/W
40
260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc.
TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2
©MMoottoororolal,aInTc.M19O9S5 Power MOSFET Transistor Device Data
1
Page 1

MTY30N50E
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min Typ Max Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0, ID = 250 µA)
Temperature Coefficient (Positive)
V(BR)DSS
500
566
— Vdc
— mV/°C
Zero Gate Voltage Drain Current
(VDS = 500 Vdc, VGS = 0 Vdc)
(VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125°C)
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0)
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)
IDSS
IGSS
µAdc
— — 10
— — 200
— — 100 nAdc
VGS(th)
2 — 4 Vdc
— 7 — mV/°C
www.DataSheet4US.ctoamtic Drain–Source On–Resistance (VGS = 10 Vdc, ID = 15 Adc)
Drain–Source On–Voltage (VGS = 10 Vdc)
(ID = 30 Adc)
(ID = 15 Adc, TJ = 125°C)
Forward Transconductance (VDS = 15 Vdc, ID = 15 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1 MHz)
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge
(See Figure 8)
(VDD = 250 Vdc, ID = 30 Adc,
VGS = 10 Vdc,
RG = 4.7 )
(VDS = 400 Vdc, ID = 30 Adc,
VGS = 10 Vdc)
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(IS = 30 Adc, VGS = 0 Vdc)
(IS = 30 Adc, VGS = 0 Vdc, TJ = 125°C)
RDS(on)
VDS(on)
gFS
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QT
Q1
Q2
Q3
VSD
— — 0.15 Ohm
— 4.1
——
Vdc
5
7
17 — — mhos
7200 10080
pF
— 775 1200
— 120 250
— 32 60 ns
— 105 175
— 160 275
— 115 200
— 235 350 nC
— 35 —
— 110 —
— 65 —
Vdc
— 0.95 1.2
— 0.88 —
Reverse Recovery Time
(See Figure 14)
(IS = 30 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
Reverse Recovery Stored Charge
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25from package to center of die)
trr
ta
tb
QRR
LD
— 485 —
ns
— 312 —
— 173 —
— 8.2 — µC
— 4.5 — nH
Internal Source Inductance
(Measured from the source lead 0.25from package to source bond pad)
(1) Pulse Test: Pulse Width 300 µs, Duty Cycle 2%.
(2) Switching characteristics are independent of operating junction temperature.
LS
— 13 — nH
2 Motorola TMOS Power MOSFET Transistor Device Data
Page 2

60
TJ = 25°C
50
40
TYPICAL ELECTRICAL CHARACTERISTICS
VGS = 10 V
6V
8V
60
VDS 10 V
50
40
MTY30N50E
30
20
10
0
0
www.DataSheet4U.com
5V
4V
2 4 6 8 10
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. On–Region Characteristics
12
30
20 100°C
TJ = – 55°C
10
25°C
0
2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
0.35
0.3 VGS = 10 V
0.25
TJ = 100°C
0.2
0.15 25°C
0.1
– 55°C
0.05
0
0 10 20 30 40 50 60
ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance versus Drain Current
and Temperature
0.17
TJ = 25°C
0.16
0.15
VGS = 10 V
0.14 15 V
0.13
0.12
0
10 20 30 40 50
ID, DRAIN CURRENT (AMPS)
60
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
2.5
VGS = 10 V
2 ID = 15 A
1.5
1
0.5
0
– 50 – 25
0 25 50 75 100
TJ, JUNCTION TEMPERATURE (°C)
125
Figure 5. On–Resistance Variation with
Temperature
150
10000
1000
TJ = 125°C
100°C
100 VGS = 0 V
10
25°C
1
0 100 200 300 400 500
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 6. Drain–To–Source Leakage
Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
3
Page 3

MTY30N50E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
www.DataSheet4thUe.cpomlateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when cal-
culating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
24000
20000
VDS = 0 V
Ciss
16000
VGS = 0 V
TJ = 25°C
12000 Crss
8000
Ciss
4000 Coss
Crss
0
10 5 0 5 10 15 20 25
VGS VDS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7a. Capacitance Variation
100000
VGS = 0 V
10000
TJ = 25°C
Ciss
1000
Coss
100 Crss
10
10 100 1000
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7b. High Voltage Capacitance
Variation
4 Motorola TMOS Power MOSFET Transistor Device Data
Page 4
Part Number TY30N50E
Manufactur Motorola
Description Search -----> MTY30N50E
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