VOICE-BAND AUDIO PROCESSOR

www.DataSheet4U.com TWL1103T-Q1 VOICE-BAND AUDIO PROCESSOR (VBAP) SGLS120A – APRIL 2002 – REVISED MAY 2002 D D D D D D D Qualification in Accordance With AEC-Q100† Qualified for Automotive Applications Customer-Specific Configuration Control Can Be Supported Along With Major-Change Approval ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (CL = 200 pF, RL = 0) 2.7-V Operation Two Differential Microphone Inputs, One Differential Earphone Output, and One Single-Ended Earphone Output Programmable Gain Amplifiers for Transmit, Receive, Sidetone, and Volume Control D D D D D D D Earphone Mute and Microphone Mute On-Chip I2C Bus, Which Provides a Simple, Standard, Two-Wire Serial Interface With Digital ICs Programmable for 15-Bit Linear Data or 8-Bit Companded (µ-Law or A-Law) Data Available in a 32-Pin Thin Quad Flatpack (TQFP) Package Designed for Analog and Digital Wireless Handsets and Telecommunications Applications Dual-Tone Multifrequency (DTMF) and Single Tone Generator Pulse Density Modulated (PDM) Buzzer Output PBS PACKAGE (TOP VIEW) description The voice-band audio processor (VBAP) is designed to perform transmit encoding analog/ digital (A/D) conversion, receive decoding digital/analog (D/A) conversion, and transmit and receive filtering for voice-band communications systems. The device operates in either the 15-bit linear or 8-bit companded (µ-law or A-Law) mode, which is selectable through the I2C interface. The VBAP generates its own internal clocks from a 2.048-MHz master clock input. AVAILABLE OPTIONS TA – 40°C to 105°C TQFP PBS PACKAGE Tube Tape and Reel PART NO. TWL1103TPBSQ1 TWL1103TPBSRQ1 TOP-SIDE MARKING TWL1103T TWL1103T 24 23 22 21 20 19 18 17 PLLVSS VSS MCLK RESET PWRUPSEL BUZZCON PCMSYN PCMCLK PLLVDD EARVSS EAR1ON EARVDD EAR1OP EARVSS EAR2O AVDD 25 26 27 28 29 30 31 32 1 2 3 4567 8 † Contact factory for details. Q100 qualification data available on request. PCMO PCMI DVSS DVDD 12 SCL 11 SDA 10 NC 9 NC 15 14 13 16 NC – No internal connection VBAP is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MBIAS MIC1P MIC1N MIC2P MIC2N REXT NC AVSS Copyright  2002, Texas Instruments Incorporated 1 TWL1103T-Q1 VOICE-BAND AUDIO PROCESSOR (VBAP) SGLS120A – APRIL 2002 – REVISED MAY 2002 functional block diagram PCMO (16) EAR1OP (29) EAR1ON (27) EAR2O (31) BUZZCON (19) Ear Amp1 Ear Amp2 PWRUPSEL (20) V SS AV DD AV SS Power and RESET DV DD DV SS (23) (32) (8) (13) (14) Digital Modulator and Filter Buzzer Control PLLV DD (25) PLLV SS (24) RX Filter and PGA g = –6 dB to +6 dB EARV DD (28) EARV SS (30, 26) RESET (21) RX Volume Control g = –18 dB to 0 dB PLL PCM Interface Sidetone g = –24 dB to –12 dB DTMF Generator TX Filter and PGA g = –10 dB to 0 dB REXT (6) MBIAS (1) MCLK (22) REF Analog Modulator Control Bus MIC Amplifier 2 g = 12 dB or 0 dB I 2C I/F SDA SCL (11) (12) MIC Amplifier 1g = 23.5 dB PCMCLK (17) PCMI (15) PCMSYN (18) MIC1P (2) MIC1N (3) MIC2P (4) MIC2N (5) 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TWL1103T-Q1 VOICE-BAND AUDIO PROCESSOR (VBAP) SGLS120A – APRIL 2002 – REVISED MAY 2002 functional description power on/reset The power for the various digital and analog circuits is separated to improve the noise performance of the device. An external reset must be applied to the active low RESET terminal to guarantee reset upon power on. After the initial power-on sequence the TWL1103 can be functionally powered up and down by writing to the power control register through the I2C interface. There is a hardwired selectable power-up terminal in default mode option. The PWRUPSEL function allows the VBAP to power up in the default mode and allows use without a microcontroller. reference A precision band gap reference voltage is generated internally and supplies all required voltage references to operate the transmit and receive channels. The reference system also supplies bias voltage for use with an electret microphone at terminal MBIAS. An external precision resistor is required for reference current setting at terminal REXT. control interface The I2C interface is a two-wire bidirectional serial interface that controls the VBAP by writing data to the six control registers: D D D D D D D D Power control Mode control Transmit PGA and sidetone control Receive PGA gain and volume control DTMF high tone DTMF low tone There are two power-up modes which may be selected at the PWRUPSEL terminal: The PWRUPSEL state (VDD at terminal 20) causes the device to power up in the default mode when power is applied. In the default mode, the I2C interface is not required, and the device may be used without an I2C interface. The programmable functions are fixed in the default modes. The PWRUPSEL state (ground at terminal 20) causes the device to go to a power-down state when power is applied. In this mode an I2C interface is required to power up the device. phase-locked loop The internal digital filters and modulators require a 10.24-MHz clock that is generated by phase locking to the 2.048-MHz master clock input. PCM interface The PCM interface transmits and receives data at the PCMO and PCMI terminals respectively. The data is transmitted or received at the PCMCLK speed once every PCMSYN cycle. The PCMCLK can be tied directly to the 2.048-MHz master clock (MCLK). The PCMSYN can be driven by an external source or derived from the master clock and used as an interrupt to the host controller. microphone amplifiers The microphone input is a switchable interface for two differential microphone inputs. The first stage is a lownoise differential amplifier that provides a gain of 23.5 dB. The second stage amplifier has a selectable gain of 0 dB or 12 dB. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TWL1103T-Q1 VOICE-BAND AUDIO PROCESSOR (VBAP) SGLS120A – APRIL 2002 – REVISED MAY 2002 functional description (continued) analog modulator The transmit channel modulator is a third-order sigma-delta design. transmit filter and PGA The transmit filter is a digital filter designed to meet CCITT G.714 requirements. The device operates in either the 15-bit linear or 8-bit companded µ-law or A-law mode that is selectable through the I2C interface. The transmit PGA defaults to 0 dB. sidetone A portion of the transmitted audio is attenuated and fed back to the receive channel through the sidetone path. The sidetone path defaults to –12 dB. The sidetone path can be enabled by writing to the power control register. receive volume control The receive volume control block acts as an attenuator with a range of –18 dB to 0 dB in 2 dB steps for control of the receive channel volume. The receive volume control gain defaults to 0 dB. receive filter and PGA The receive filter is a digital filter that meets CCITT G.714 requirements with a high-pass filter that is selectable through the I2C interface. The device operates in either the 15-bit linear or 8-bit µ-law or A-law companded mode, which is selectable through the I2C interface. The gain defaults to –1 dB representing a 3-dBm0 level for a 32-Ω load impedance and the corresponding digital full scale PCMI code. The gain may be set to –2 dB for the respective 3-dBm0 level for a 16-Ω load impedance. digital modulator and filter The second-order digital modulator and filter convert the received digital PCM data to the analog output required by the earphone interface. earphone amplifiers The analog signal can be routed to either of two earphone amplifiers, one with differential output (EAR1ON and EAR1OP) and one with single-ended output (EAR2O). Clicks and pops are suppressed for EAR1 differential output only. tone generator The tone generator provides generation of standard DTMF tones and single tone frequencies which are output to the following devices: 1) The buzzer driver, as a pulse density modulation (PDM) signal 2) The receive path digital/analog converter (DAC) for outputting through the earphone. There are 255 possible single tones. The tone integer value is determined by the following formula: Round (Tone Freq (Hz)/7.8135 Hz) The value is loaded into one of two 8-bit registers, the high-tone register (04), or the low-tone register (05). The tone output is 2 dB higher when applied to the high-tone register (04). When generating DTMF tones, the high DTMF tone must be applied to the high-tone register and the low frequency tone to the low-tone register. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TWL1103T-Q1 VOICE-BAND AUDIO PROCESSOR (VBAP) SGLS120A – APRIL 2002 – REVISED MAY 2002 Terminal Functions TERMINAL NAME AVDD AVSS BUZZCON DVDD DVSS EAR1ON EAR1OP EAR2O EARVDD EARVSS MBIAS MCLK MIC1P MIC1N MIC2P MIC2N PCMI PCMO PCMSYN PCMCLK PLLVSS PLLVDD PWRUPSEL REXT RESET SCL SDA NO. µBGA A1 J1 F9 J6 J7 A6 A4 A2 A5 A3, A7 B1 C9 C1 D1 E1 F1 J8 J9 G9 H9 A9 A8 E9 G1 D9 J5 J4 PBS 32 8 19 13 14 27 29 31 28 30, 26 1 22 2 3 4 5 15 16 18 17 24 25 20 6 21 12 11 I I O I I O O O I I O I I I I I I O I I I I I I/O I I I/O Analog positive power supply Analog negative power supply Buzzer output, a pulse-density modulated signal to apply to external buzzer driver Digital positive power supply Digital negative power supply Earphone 1 amplifier output (–) Earphone 1 amplifier output (+) Earphone 2 amplifier output Analog positive power supply for the earphone amplifiers Analog negative power supply for the earphone amplifiers Microphone bias supply output, no decoupling capacitors Master system clock input (2.048 MHz) (digital) MIC1 input (+) MIC1 input (–) MIC2 input (+) MIC2 input (–) Receive PCM input