VAN Data Link Controller

Features • • • • • • • • • • • • • • • • Fully Compliant to VAN Specification ISO/11519-3 Handles All Specified Module Types Handles All Specified Message Types Handles Retransmission of Frames on Contention and Errors 3 Separate Line Inputs with Automatic Diagnosis and Selection Normal or Pulsed (Optical and Radio Mode) Coding VAN Transfer Rate: 1 Mbit/s Maximum SPI/SCI Interface – SPI Transfer Rate: 4 Mbit/s Maximum – SCI Transfer Rate: 125 Kbit/s Maximum Idle and Sleep Modes 128 Bytes of General-purpose RAM 14 Identifier Registers with All Bits Individually Maskable 6-source Maskable Interrupt, Including an Interrupt-on-reset to Detect Glitches on the Reset Pin Integrated Crystal or Resonator Oscillator with Internal Baud Rate Generator and Buffered Clock Output Single +5V Power Supply 0.8 µm CMOS Technology SO16 Package VAN Data Link Controller with Serial Interface TSS463-AA Description The TSS463AA is a circuit that allows the transfer of all the status information needed in a car or truck over a single low-cost wire pair, that minimizes electrical wire usage. It can be used to interconnect powerful functions to control and interface car body electronics (lights, wipers, power window, etc.). The TSS463AA is fully compliant with the VAN ISO Standard 11519-3. This standard supports a wide range of applications such as low-cost remote-controlled switches. Typically it is used for lamp control, complex, highly-autonomous, distributed systems, which require fast and secure data transfers. The TSS463AA is a microprocessor-interfaced line controller for mid- to high-complexity bus-masters and listeners like dashboard controllers, car stereo or mobile telephone CPUs. The microprocessor interface consists of a 256-byte RAM and a register area divided into 11 control registers, 14 channel register sets and 128 bytes of general purpose RAM, used as a message storage area, and a 6-source maskable interrupt. The circuit operates in the RAM using DMA techniques, controlled by the channel and control registers. This allows virtually any microprocessor, including SPI/SCI interface, to be connected easily to the TSS463AA. Messages are encoded in enhanced Manchester code, and an optional pulsed code for use with an optical or radio link, at a maximum bit rate of 1 Mbit/s. The TSS463AA analyzes the messages received or transmitted according to 6 different criteria including some higher level checks. In addition, the bus interface has three separate inputs with automatic source diagnosis and selection. The interface allows for multibus listening or the automatic selection of the most reliable source at any time if several line receivers are connected to the same bus. www.DataSheet4U.com 4205B–AUTO–12/04 1 Block Diagram 2 TSS463-AA 4205B–AUTO–12/04 TSS463-AA Pin Configuration TOP VIEW 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 MISO SS INT VDD XTAL1 XTAL2 TEST/VSS CKOUT MOSI SCLK RESET GND TXD RXD0 RXD2 RXD1 Pin Description I/O Type O 3-state I trigger CMOS Open-drain Power I CMOS O Ground O I CMOS Pull-down I CMOS Pull-down I CMOS Pull-down O 3-state Ground I trigger CMOS pull-up I trigger CMOS I trigger CMOS Pin Name MISO SS INT VDD XTAL1 XTAL2 TEST/VSS CKOUT RXD1 RXD2 RXD0 TXD GND RESET SCLK MOSI Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Hardware Reset (active low) SPI/SCI Clock Input SPI/SCI Data Input Pin Function SPI/SCI Data Output SPI/SCI Slave Select (active low) Interrupt (active low) + 5V power supply Crystal oscillator or clock input pin from 1 to 16 MHz Crystal oscillator output pin Test mode input Buffered clock output VAN bus input 1 VAN bus input 2 VAN bus input 0 VAN bus output 3 4205B–AUTO–12/04 Application The TSS463AA is a microprocessor controlled line controller for the VAN bus. It can interface to virtually any microprocessor which includes SPI or SCI interface. • • • The TSS463AA provides one full Motorola compatible SPI interface. It includes one full compatible Intel UART (mode 0 only). And finally, one 9-bits SCI interface is also integrated. In addition, the circuit features a single interrupt pin. This pin can be treated as level sensitive. For example, if there is a pending interrupt inside the circuit when another interrupt is reset, the INT pin will emit a high pulse with the same pulse width as the internal write strobe (typically 20 ns). Figure 1. Typical Application With Motorola SPI Mode Remaining pins SCLK MOSI MISO(2) PORT X.Y IRQ General I/O (if needed) 100K MISO 1 SS INT 2 16 15 SCLK RESET (1) mC Microcontroller MOSI TSS463 3 VDD 4 5 6 14 13 12 11 10 9 RxD0 RxD2 RxD1 VAN Bus GND TxD CKOUT XTAL1 XTAL2 RESET (1) TEST/VSS 7 CKOUT 8 Notes: 1. The TSS463AA RESET pin can either be connected to GND through a 1 µF capacitor, or the µC RESET pin or unconnected (inactive with internal pull-up). 2. Leaving MISO output pin floating in high impedance mode slightly increases standby consumption. A 100 KΩ pull-up/pull-down resistor is recommended. 4 TSS463-AA 4205B–AUTO–12/04 TSS463-AA Microprocessor Interface Interface Modes Motorola SPI Mode The processor controls the TSS463AA by reading and writing the internal registers of the circuit. These registers appear to the processor as regular memory locations. The TSS463AA must be connected with an SPI or SCI serial interface. The following section provides information on switching from one mode to another. The first two bytes to be sent by the master (CPU) are called “Initialization Sequence”: This sequence provides a proper asynchronous RESET in the TSS463AA and it selects the Motorola SPI, Intel SPI or the SCI serial mode. This initialization sequence is shown on Figure 4. Two 0x00 will cause an internal RESET and assert the Motorola SPI mode, Two “0xFF” will provide an internal RESET and assert the Intel® SPI mode and “9 bits to 0 followed by 0xFF or 0xFE” will generate an internal RESET and assert the 9-bits SCI mode. Figure 2. Mode Configuration Byte SPI 8 Pulses SCLK MOSI 0x00 or 0xFF 0x00 0xFF Motorola Intel SS Internal RESET Internal RESET and SPI Mode (Intel or Motorola) SCI 9 Pulses SCLK MOSI 0 . 0000 . 0000 1 . 1 . 1111 111 SS Internal RESET Internal RESET and SCI Mode The Motorola Serial Peripheral Interface (SPI) is fully compatible with the SPI Motorola protocol. The interface is implemented for slave-mode only (the TSS463AA can not generate SPI frames by itself). The SPI interface allows the interconnection of several CPUs and peripherals on the same printed circuit board. The SPI mode interface consists of 4 pins: separate wires are required for data and clock, so the clock is not included in the data stream as shown in Figure 5. One pin is needed for the serial clock (SCLK), two pins for data communication MOSI and MISO and one pin for Slave Select (SS). 5 4205B–AUTO–12/04 Figure 3. SPI Data Stream SPI 8 Pulses SCLK MOSI 0x55 MISO 0x66 SS SCLK: Serial Clock The master device provides the serial clock for the slave devices. Data is transferred synchronously with this clock in both directions. The master and the slave devices send/receive a data byte during an eight-clock pulse sequence. The MOSI pin is the master device data output (CPU) and the slave device data input (TSS463AA). Data is transferred serially from the master to the slave on this line; most significant bit (MSB) first, least significant bit (LSB) last. The MISO pin is configured as the slave device data output (TSS463AA) and as master device data input (CPU). When the slave device is not selected (SS = 1), this pin is in high impedance state. The SS pin is the slave chip select. It is low active. A low state on the Slave Select input allows the TSS463AA to accept data on the MOSI pin and send data on the MISO pin. The Slave Select signal must not toggle between each transmitted byte and should be left at a low level during the whole SPI frame. SS must be asserted to inactive high level at the end of the SPI frame. As mentioned before, if SS is not asserted, MISO pin is in a high impedance state and incoming data is not driven to the serial data register. MOSI: Master Out Slave In MISO: Master In Slave Out SS: Slave Select SPI Protocol The general format of the data communication in the SPI frame between the TSS463AA and the host is a bit-for-bit exchange on each SCLK clock pulse. Data is arranged in the TSS463AA such that the significance of a bit is determined by its position from the start for output and from the end for input, most significant bit (MSB) is sent first. Bit exchanges in multiples of 8 bits are allowed. The Idle Clock Polarity (CPOL) and the Clock Phase (CPHA) are not programmable: the CPOL and CPHA values to be programmed in the master (CPU) are CPOL = CPHA = 1. This is available for all modes. Waveforms with transmit and sample points are shown in Figure 6. 6 TSS463-AA 4205B–AUTO–12/04 TSS463-AA Figure 4. CPOL and CPHA in the TSS463AA CPOL = CPHA = 1 Data Sample Points SPI 8 Pulses SCLK MOSI MISO SS 0x55 0x66 Data Transmit Points At the beginning of a transmission over the serial interface, the first byte is the address of the TSS463AA register to be accessed. The next byte transmitted is the control byte which determines the direction of the communication. The following bytes are data bytes (consecutive bytes are written in or read from Address, Address + 1, Address + 2,..., Address + n with n = 0 to 28). To make sure the TSS463AA is not out of synchronization, the SPI interface will transmit data “0xAA" and "0x55” on the MISO pin during address and control byte time. This way, the master always ensures the TSS463AA is well-synchronized. If the TSS463AA is out of synchronization, the master can assert the SS pin inactive to re synchronize the SPI interface or can assert the RESET pin active or can send an initialization sequence. When the SS pin is inactive, the SCLK is allowed to toggle. This will have no e