VAN Data Link Controller

Features • • • • • • • • • • • • • • • • • • Fully Compliant to VAN Specification ISO/11519-3 Handles All Specified Module Types Handles All Specified Message Types Handles Retransmission of Frames on Contention and Errors 3 Separate Line Inputs with Automatic Diagnosis and Selection 1 Mbit/s Maximum Transfer Rate Normal or Pulsed (Optical and Radio Mode) Coding Intel®, NEC®, Texas Instruments® and Motorola® Compatible 8-bit Microprocessor Interface Multiplexed Address and Data Bus Idle and Sleep Modes 128 Bytes of General-purpose RAM DMA Capabilities for Message Handling 14 Identifier Registers with All Bits Individually Maskable 6-source Maskable Interrupt, Including an Interrupt-on-reset to Detect Glitches on the Reset Pin Integrated Crystal or Resonator Oscillator with Internal Baud Rate Generator and Buffered Clock Output Single +5V Power Supply 0.8 µm CMOS Technology SO24 Package VAN Data Link Controller TSS461C Description Cost optimization in car manufacturing is of extreme importance today. Solutions to this problem often implies the use of more advanced and intelligent electronic circuits. The TSS461C is a circuit which allows the transfer of all the status information needed in a car or truck over a single low-cost wire pair, thatwww.DataSheet4U.comthe electrical wire minimizes usage. It can be used to interconnect powerful functions (ABS, dashboard, power train control) and to control and interface car body electronics (lights, wipers, power window, etc.). The TSS461C is fully compliant with the ISO Standard 11519-3. This standard supports a wide range of applications such as low-cost remote-control switches. Typically it is used for lamp control; complex, highly-autonomous, distributed systems like engine controls, which require fast and secure data transfers. The TSS461C is a microprocessor-interfaced line controller for mid-to-high complexity bus-masters and listeners like injection/ignition control calculators, dashboard controllers and car stereo or mobile telephone CPUs. The microprocessor interface consists of a 256-bytes of RAM and a register area divided into 11 control registers, 14 channel register sets and 128 bytes of general purpose RAM, used as a message storage area, and a 6-source maskable interrupt. The circuit operates in RAM using DMA techniques, controlled by the channel and control registers. This allows virtually any microprocessor to interface with ease to the TSS461C, and to use the free RAM as a scratch pad. Messages are encoded in enhanced Manchester code, and an optional pulsed code for use with an optical or radio link, at a maximum bit rate of 1 Mbit/s. The TSS461C analyzes the messages received or transmitted according to 6 different criteria including some higher level checks. In addition, the bus interface has three separate inputs with automatic source diagnosis and selection, that allows for multibus listening or the automatic selection of the most reliable source at any time if several line receivers are connected to the same bus. 4193G–AUTO–12/04 1 Block Diagram AD[7:0] ALE INT RESET TEST VCC GND Address and Data Bus Multiplexing logic control bus data bus address bus status bus 128 bytes Message buffer RAM Protocol controller state machine and ID registers Status and control registers Reception logic Source diagnosis and selection logic Data serializer and deserializer CRC generator and checker Clock generator and line synchronization logic Transmission logic XTAL1 XTAL2 CKOUT TxD RxD0 RxD1 RxD2 2 TSS461C 4193G–AUTO–12/04 TSS461C Pin Configuration TOP VIEW 24 Pin SOP AD4 AD5 AD6 AD7 VCC INT ALE (E) CS XTAL1 XTAL2 Test/VSS CKOUT Note: 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 AD3 AD2 AD1 AD0 VSS RESET TXD RXD0 RXD2 RXD1 WR (R/W) RD (VSS) 1. The names in parenthesis refer to the functionalities in Motorola mode. I/O Type Pin Name AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 Pin Number 21 22 23 24 1 2 3 4 7 13 14 8 6 Pin Function I/O TTL Multiplexed address and data bus. The address is latched on the falling address of ALE. I Trigger TTL ALE RD (VSS) WR (R/W) CS(E) Address Latch Enable Read Command Write Command Chip Select (active high) Interrupt Asynchronous general reset glitch filtered (12 ns) Open-drain I Trigger CMOS Pull-down INT RESET 19 3 4193G–AUTO–12/04 I/O Type Pin Name RXD0 RXD1 RXD2 Pin Number 17 15 16 18 9 10 12 11 5 20 Pin Function I CMOS Pull-down VAN bus Inputs 3-state I 0 0 Ground Power Ground TXD XTAL1 XTAL2 CKOUT TEST/VSS VCC VSS VAN bus Output Crystal oscillator or clock input pins Buffered clockout output enabled if no reset Oscillator Ground +5V Power Supply 4 TSS461C 4193G–AUTO–12/04 TSS461C Operation The TSS461C is a microprocessor-controlled line controller for the VAN bus. It can interface to virtually any microprocessor, but the I/O signals of the circuit have been optimized to use with the TSC51/TSC251 series of microcontrollers. It features a multiplexed address and data bus, controlled by an address strobe pin ALE and separated read RD and write WR command pins. The address is latched on the falling edge of ALE. The circuit also features one single interrupt pin. This pin can be treated as level or edge sensitive, For example, if there is a pending interrupt inside the circuit when another interrupt is reset, the INT pin will emit a high pulse with the same pulse width as the internal write strobe (typically 20 ns). Figure 1. Typical Application VAN Bus Remaining Pins General I/O TSS461C Series Microcontroller C1 33 pF DATA P3.6/WR P3.7/RD ALE WR RD TXD Differential + RXD0 ALE P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 RESET XTAL1 INT VCC AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 VAN DLC RXD1 RXD2 DATA + - VREF CS DATA + VAN Line Driver & Receivers INT CKOUT RESET DATA GND XTAL1 XTAL2 GND 5 4193G–AUTO–12/04 Microprocessor Interface Interface Modes The processor controls the TSS461C by reading and writing the internal registers of the circuit. These registers appear to the processor as regular memory locations. The TSS461C must be plugged in an Intel or Motorola environment with an 8-bit address/data bus multiplexed. Table 1. Access Mode Logic CS (E) 0 1 1 1 1 0 0 1 1 0 1 0 1 RD WR (R/W) Operation Mode No operation Write Operation in Motorola mode Read operation in both modes Write operation in Intel mode No operation In Intel environment, access operations need CS active, a read one with RD active, a write one with WR active. If TSS461C is the single peripheral in the processor space, CS can be wired to VCC. In Motorola environment, the RD pin is wired to VSS and the access operations are driven by CS (E). Contrary to Intel mode, CS (E) must never be wired to VCC even if the TSS461C is alone. To switch on-the-fly from one mode to the other, CS must be inactive. Intel Mode The Intel mode interface consists of 13 pins. 8 pins are the multiplexed address and data bus, and the rest are the address strobe, the read and write commands, the chip select and the interrupt request pins. To access the memory locations in Intel mode, the processor must first assert a valid address on the multiplexed address and data bus and drive the address strobe pin high. When the required setup time has passed, the processor must drive the address strobe low, and keep the address valid for the required hold time. The processor must then either assert the data to be written on the address and data bus, if a write is intended, or float the data bus for a read. The next step is to drive either the write or read command pins low, according to the function required, and at the same time drive the chip select pin high. The TSS461C access cycle is then terminated by driving the chip select and command pins low. Note: that the chip select pin may be driven high for the entire access cycle, and may also remain high during and after the termination of the cycle. 6 TSS461C 4193G–AUTO–12/04 TSS461C Figure 2. Intel Read and Write Cycles ALE DATA TO BE WRITTEN DATA READ AD[7:0] ADDRESS ADDRESS RD WR CS WRITE CYCLE READ CYCLE Motorola Mode In Motorola mode, the WR pin becomes the R/W command, the RD pin must be connected to ground and the CS pin becomes the E strobe. There is no separate chip select input. For example, if some external decoder is used, this decoder should not drive the E input high unless the processors E output is high as well. See Figure 3 for the Motorola read and write cycles. The main difference between Intel and Motorola mode is that the timing in Intel mode is referenced to the command signals (RD and WR), but in Motorola mode the reference is the E signal. Figure 3. Motorola Read and Write Cycles ALE DATA TO BE WRITTEN DATA READ AD[7:0] ADDRESS ADDRESS VSS (RD) R/W (WR) E (CS) WRITE CYCLE READ CYCLE Interrupts If an event occurs in the TSS461C that needs the attention of the processor, this will be signalled on the active low, open-drain interrupt request pin. The events that create this request are controlled by the internal registers. Every time the microprocessor accesses any of the interrupt registers (addresses 0x08 to 0x0B), the INT pin will be released momentarily. This enables the TSS461C to work with processors that either have edge or level sensitive interrupt inputs. 7 4193G–AUTO–12/04 Reset The reset is applied asynchronously regarding XTAL clock. It can be done either by the RESET pin or by software. The RESET pin is a CMOS trigger input with a pull-down resistor (110 kΩ). An external 1 µF capacitor to VCC provides to RESET pin an efficient behavior. The software reset is made through the GRES command bit of the Command Register (0x03). The two resets are ored, filtered and gauged. Then the internal reset, always asserted asynchronously, enables the internal oscillator. Then it waits for eight clock periods for the oscillator stability. The different blocks of the T