5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER

www.DataSheet4U.com TSB14C01 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER SLLS231B – MARCH 1996 – REVISED MAY 1997 D D D D D D Supports Provisions of IEEE 1394-1995 (1394) Standard for High-Performance Serial Bus† Fully Interoperable With FireWire™ Implementation of 1394 Provides A Backplane Environment That Supports 50 or 100 Megabits per Second (Mbits/s) Logic Performs System Initialization and Arbitration Functions Encode and Decode Functions Included for Data-Strobe Bit-Level Encoding Incoming Data Resynchronized to Local Clock D D D D D D Separate Transmitter and Receiver for Greater Flexibility Data Interface to Link-Layer Controller (Link) Provided Through Two Parallel Signal Lines at 25/50 MHz 100-MHz or 50-MHz Oscillator Provides Transmit, Receive-Data, and Link Clocks at 25/50 MHz Single 5-V Supply Operation Packaged in a High-Performance 64-Pin TQFP (PM) Package for 0°C to 70°C Operation Packaged in a 68-Pin CFP (HV) Package for – 55°C to 125°C Operation description The TSB14C01 provides the transceiver functions needed to implement a single port node in a backplanebased 1394 network. The TSB14C01 provides two terminals for transmitting, two terminals for receiving, and a single terminal to externally control the drivers for data and strobe. The TSB14C01 is not designed to drive the backplane directly, this function must be provided externally. The TSB14C01 is designed to interface with a link-layer controller (link), such as the TSB12C01A. The TSB14C01 requires an external 98.304-MHz or 49.152-MHz reference oscillator input for S100/50 operation. The reference signal is internally divided to provide the 49.152-MHz ±100-ppm system clock signals used to control transmission of the outbound encoded strobe and data information. The 49.152-MHz clock signal is supplied to the associated link for synchronization of the two chips, when this device is in the S100 mode of operation, OSC_SEL is asserted high. When the TSB14C01 is in the S50 mode of operation, the clock rate supplied to the link is 24.576 MHz. Data bits to be transmitted are received from the link on two parallel paths and are latched internally in the TSB14C01 in synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded, and then transmitted at 98.304-Mbits/s (in S100 mode) as the outbound data-strobe information stream. During transmission, the encoded data information is transmitted on TDATA, and the encoded strobe information is transmitted on TSTRB. During packet reception the encoded information is received on RDATA and strobe information on RSTRB. The received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The serial data bits are split into two parallel streams, resynchronized to the local system clock, and sent to the associated link. The TSB14C01 is a 5-V device and provides CMOS-level outputs. AVAILABLE OPTIONS PACKAGES TA 0°C to 70°C – 55°C to 125°C CERAMIC FLAT PACK (HV) — TSB14C01MHV THIN QUAD FLAT PACK (PM) TSB14C01PM — Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. † This serial bus implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thomson, Limited. FireWire is a trademark of Apple Computer, Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1997, Texas Instruments Incorporated POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TSB14C01 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER SLLS231B – MARCH 1996 – REVISED MAY 1997 PM PACKAGE (TOP VIEW) ARB_CLK PHYENA VCC ENA_PRI VCC N_POR GND LREQ VCC SCLK TSCLK GND CTL0 CTL1 D0 D1 1 2 3 4 5 6 7 8 9 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 OSC_SEL GND NC NC NC NC NC RDATA RSTRB VCC TDATA TSTRB GND N_OEB_D GND PTEST_INDRV VCC NC 10 11 12 13 14 15 33 16 1718 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NC – No connection 2 VCC EN_EXID EN_EXPRI EX_ID5 EX_ID4 EX_ID3 EX_ID2 EX_ID1 EX_ID0 GND EX_PRI3 EX_PRI2 EX_PRI1 EX_PRI0 NC NC POST OFFICE BOX 655303 GND RPREFIX VCC VCC GND VCC TI1 VCC NC XI_50 GND NC XI_100 GND TSB14C01 • DALLAS, TEXAS 75265 TSB14C01 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER SLLS231B – MARCH 1996 – REVISED MAY 1997 HV PACKAGE (TOP VIEW) NC ARB_CLK PHYENA VCC ENA_PRI VCC N_POR GND LREQ VCC SCLK TSCLK GND CTL0 CTL1 D0 D1 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 NC GND RPREFIX VCC VCC GND VCC TI1 VCC NC XI_50 GND NC XI_100 GND OSC_SEL GND 87 6 5432 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 TSB14C01M 52 51 50 49 48 47 46 45 26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 NC NC NC NC NC RDATA RSTRB VCC TDATA TSTRB GND N_OEB_D GND PTEST_INDRV VCC NC NC NC – No connection VCC EN_EXID EN_EXPRI EX_ID5 EX_ID4 EX_ID3 EX_ID2 EX_ID1 EX_ID0 GND EX_PRI3 EX_PRI2 EX_PRI1 EX_PRI0 NC NC NC POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TSB14C01 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER SLLS231B – MARCH 1996 – REVISED MAY 1997 system block diagram N_OEB_D D0 – D1 2 / 2 TSB14C01 Tdata Rdata Tstrb Rstrb BPdata Host Interface 1394 LinkLayer Controller CTL0 – CTL1 / LREQ 1394 Backplane PhysicalLayer Controller BPstrb SCLK NOTE A: The backplane transceiver is customer supplied and is different for each type of backplane. functional block diagram SCLK D0, D1 Data Encode SCLK Physical ID Pr0 – Pr3 2 D0 – D1 CTL0 – CTL1 LREQ LINK/PHY Interface Fair/Urg Req Iso Req Cycle Req Ack Req Arb Won Arb Lost Arb Res Gap Sub Act Gap Ack Gap Bus Reset CLK (see Note A) CLK CLK RxStb RxData Data Resync/ Decode RSTRB RDATA ARB Control TxArbStrb TxArbData CLK TxPktStrb TxPktData ARB/DATA MUX TSTRB TDATA / 2 / RxData RxCLK RxCLK NOTE A: CLK is either terminal XI_50 or XI_100 depending on the mode selection. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TSB14C01 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER SLLS231B – MARCH 1996 – REVISED MAY 1997 Terminal Functions TERMINAL NAME ARB_CLK PM NO. 1 HV NO. 11 TYPE TTL I/O O DESCRIPTION Arbitration clock. ARB_CLK is the clock used for arbitration. ARB_CLK is for test and debug. It can be put into a high-impedance state by PTEST_INDRV. This terminal is not used in normal operation and is always at 49.152 MHz. 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