(TSA5526 / TSA5527) 1.3 GHz universal bus-controlled TV synthesizers

INTEGRATED CIRCUITS DATA SHEET TSA5526; TSA5527 1.3 GHz universal bus-controlled TV synthesizers Product specification Supersedes data of 1995 Mar 22 File under Integrated Circuits, IC02 1996 Sep 24 Philips Semiconductors Product specification 1.3 GHz universal bus-controlled TV synthesizers FEATURES • Complete 1.3 GHz single chip system • Four PNP band switch buffers (40 mA) • 33 V output tuning voltage • In-lock detector • 5-step ADC • 15-bit programmable divider • Programmable reference divider ratio (512, 640 or 1024) • Programmable charge-pump current (60 or 280 µA) • Programmable automatic charge-pump current switch • Varicap drive disable • Universal bus protocol I2C-bus or 3-wire bus: – bus protocol for 18 or 19 bits transmission (3-wire bus) – extra protocol for 27 bits for test and features (3-wire bus) – address plus 4 data bytes transmission (I2C-bus write mode) – address plus 1 status byte transmission (I2C-bus read mode) – three independent I2C-bus addresses • Low power and low radiation. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TSA5526M TSA5526T TSA5527M TSA5527T TSA5526AM TSA5526AT TSA5527AM TSA5527AT SSOP16 SO16 SSOP16 SO16 SSOP16 SO16 SSOP16 SO16 DESCRIPTION APPLICATIONS TSA5526; TSA5527 • TV tuners and front ends • VCR tuners. VERSION SOT369-1 SOT109-1 SOT369-1 SOT109-1 SOT369-1 SOT109-1 SOT369-1 SOT109-1 plastic shrink small outline package; 16 leads; body width 4.4 mm plastic small outline package; 16 leads; body width 3.9 mm plastic shrink small outline package; 16 leads; body width 4.4 mm plastic small outline package; 16 leads; body width 3.9 mm plastic shrink small outline package; 16 leads; body width 4.4 mm plastic small outline package; 16 leads; body width 3.9 mm plastic shrink small outline package; 16 leads; body width 4.4 mm plastic small outline package; 16 leads; body width 3.9 mm 1996 Sep 24 2 Philips Semiconductors Product specification 1.3 GHz universal bus-controlled TV synthesizers QUICK REFERENCE DATA SYMBOL VCC1 VCC2 ICC1 ICC2 fRF Vi(RF) PARAMETER supply voltage (+5 V) band switch supply voltage (12 V) supply current band switch supply current RF input frequency RF input voltage fi = 80 to 150 MHz fi = 150 to 1000 MHz fi = 1000 to 1300 MHz fxtal Io(PNP) Ptot Tstg Tamb Notes 1. One band switch buffer ON, Io = 40 mA. crystal oscillator input frequency PNP band switch buffers output current total power dissipation storage temperature operating ambient temperature note 2 note 3 note 1 CONDITIONS MIN. 4.5 VCC1 − − 64 −25 −28 −15 3.2 4 − −40 −20 TSA5526; TSA5527 TYP. − 12 20 50 − − − − 4.0 − 250 − − MAX. 5.5 13.5 25 55 1300 3 3 3 4.48 50 400 +150 +85 V V UNIT mA mA MHz dBm dBm dBm MHz mA mW °C °C 2. One band switch buffer ON, Io = 40 mA; two buffers ON, maximum sum of Io = 50 mA. 3. The power dissipation is calculated as follows: P D = V CC1 × I CC1 + V CC2 × ( I CC2 – I o ) + I o × V CE ( satPNP ) + ( V33 ⁄ 2 ) ⁄ 27 kΩ. 2 1996 Sep 24 3 Philips Semiconductors Product specification 1.3 GHz universal bus-controlled TV synthesizers GENERAL DESCRIPTION The device is a single-chip PLL frequency synthesizer designed for TV and VCR tuning systems. The circuit consists of a divide-by-eight prescaler with its own preamplifier, a 15-bit programmable divider, a crystal oscillator and its programmable reference divider and a phase/frequency detector combined with a charge-pump which drives the tuning amplifier and the 33 V output. Four high-current PNP band switch buffers are provided for band switching. Two PNP buffers can be switched on simultaneously. The sum of the collector currents is limited to 50 mA. Depending on the reference divider ratio (512, 640 or 1024), the phase comparator operates at 3.90625 kHz, 6.25 kHz or 7.8125 kHz using a 4 MHz crystal. The device can be controlled in accordance with the I2C-bus format or the 3-wire bus format depending on the voltage applied to the SW input (see Table 2). In the 3-wire bus mode (SW = HIGH) pin 12 is the LOCK output. The lock output is LOW when the PLL loop is locked. In the I2C-bus mode (SW = LOW) the LOCK detector bit FL is set to logic 1 when the loop is locked and is read on the SDA line (status byte) during a read operation. The ADC input is available on pin 12 for AFC control in the I2C-bus mode only. The ADC code is read during a read operation on the I2C-bus. In the test mode pin 12 is used as a test output for fref and 1⁄2fdiv in the I2C-bus mode and the 3-wire bus mode (see Table 6). When the automatic charge-pump current switch mode is activated, depending on the device given in Table 6, and when the loop is phase-locked, the charge-pump current value is automatically switched to LOW. Table 1 Differences between TSA5526 and TSA5527 DATA WORD 18-bit 19-bit 19-bit TSA5526; TSA5527 This action is taken to improve the carrier-to-noise ratio. The status of this feature can be read in the ACPS flag during a read operation on the I2C-bus (see Table 8). I2C-bus format (SW = LOW) Five serial bytes (including address byte) are required to address the device, select the VCO frequency, program the four PNP band switch buffers, set the charge-pump current and the reference divider ratio. The device has three independent I2C-bus addresses which can be selected by applying a specific voltage on the CE input (see Table 5). The general address C2 is always valid. When the I2C-bus format is fully used, TSA5526 and TSA5527 are equal. 3-wire bus format (SW = VCC1 or open-circuit) Data is transmitted to the device during a HIGH level on the CE input (enable line pin 15). The device is compatible with 18-bit and 19-bit data formats. The first four bits are used to program the PNP band switch buffers and the remaining bits are used to control the programmable divider. A 27-bit data format may also be used to set the charge-pump current, the reference divider ratio and for test purposes. The differences between TSA5526 and TSA5527 are given in Table 1. When the 27-bit format is used, the TSA5526 and TSA5527 are equal and the reference divider is controlled by the RSA and RSB bits (see Table 7 and Figs 3, 4 and 5). TYPE NUMBER TSA5526 TSA5526 TSA5527 Notes REFERENCE DIVIDER 512(1) 1024(1) 640(2) FREQUENCY STEP (kHz) 62.5 31.25 50 1. The selection of the reference divider is given by an automatic identification of the data word length. 2. The reference divider is set to 640 at power-on reset. 1996 Sep 24 4 1996 Sep 24 9 CP V tune 10 f div DIVIDER 512/640/1024 f ref CP RSA RSB T2,T1,T0 15-BIT FREQUENCY REGISTER IN-LOCK DETECTOR LOGIC lock RSA,RSB 3 OS 4-BIT BAND SWITCH REGISTER GATE 7-BIT CONTROL REGISTER 2 VCC1 VEE AMP BLOCK DIAGRAM Philips Semiconductors handbook, full pagewidth RF 1 PRESCALER DIVIDE-BY-8 CHARGE PUMP 15-BIT PROGRAMMABLE DIVIDER 16 XTAL XTAL OSCILLATOR DIGITAL PHASE COMPARATOR 1.3 GHz universal bus-controlled TV synthesizers POWER-ON RESET 13 SCL 14 5 T2,T1,T0 4 VCC2 BS1 BS2 BS3 BS4 8 7 6 5 SDA 15 I 2 C/3-WIRE BUS TRANSCEIVER CE SW 11 5-LEVEL ADC 12 TSA5526 TSA5527 MBE327 LOCK/ ADC TSA5526; TSA5527 Product specification Fig.1 Block diagram. Philips Semiconductors Product specification 1.3 GHz universal bus-controlled TV synthesizers PINNING SYMBOL RF VEE VCC1 VCC2 BS4 BS3 BS2 BS1 CP Vtune SW LOCK/ADC SCL SDA CE XTAL PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ground supply voltage (+5 V) band switch supply voltage (+12 V) PNP band switch buffer output 4 PNP band switch buffer output 3 PNP band switch buffer output 2 PNP band switch buffer output 1 charge-pump output tuning voltage output bus format selection input, I2C-bus or 3-wire lock detector output (3-wire bus/ ADC input (I2C-bus) serial clock input serial data input/output chip enable/address selection input crystal oscillator input handbook, halfpage TSA5526; TSA5527 DESCRIPTION RF signal input RF VEE V CC1 VCC2 BS4 BS3 BS2 BS1 1 2 3 4 5 6 7 8 MBE326 16 XTAL 15 CE 14 SDA TSA5526 TSA5527 13 SCL 12 LOCK/ADC 11 SW 10 V tune 9 CP Fig.2 Pin configuration. FUNCTIONAL DESCRIPTION The device is controlled via the I2C-bus or the 3-wire bus depending on the voltage applied to the SW input (pin 11). A HIGH level on the SW input enables the 3-wire bus inputs which are CE (Chip Enable), SDA (serial data input) and SCL (serial clock input). A LOW level on the SW input enables the I2C-bus inputs which are AS (Address Selection input), SDA (serial data input/output) and SCL (serial clock input). The bus format selection is given in Table 2. I2C-bus mode (SW = LOW); see Table 3 WRITE MODE (R/W = 0) Data bytes can be sent to the device after the address transmission (first byte). Four data bytes are required to fully program the device. The bus transceiver has an auto-increment facility which permits the programming of the device within one single transmission (address + 4 data bytes). The device can also be partially programmed providing that the first data byte following the address is Divider Byte 1 (DB1) or the Control Byte (CB). The bits in the data bytes are defined in Table 3. The first bit of the first data byte transmitted indicates whether frequency data (first bit = logic 0) or control and band switch data (first bit = logic 1) will follow. Until an I2C-bus STOP command is sent by the controller, additional data bytes can be entered without the need to readdress the device. The frequency register is loaded after the 8th clock pulse of the second Divider Byte (DB2), the control register is loaded after the 8th clock pulse of the Control Byte (CB) and the band switch register is loaded after the 8th clock pulse of the Band switch Byte (BB). I2C-BUS ADDRESS SELECTION The module address contains programmable address bits (MA1 and MA0) which offer the possibility of having several synthesizers (up to 3) in one system by applying a specific voltage to the CE input. The relationship between MA1 and MA0 and the input vo