Description
Typical Size (6,3 mm x 6,4 mm) www.ti.com TPS54310 Q1 SGLS280B − JANUARY 2005 − REVISED FEBRUARY 2007 3 V TO 6 V INPUT, 3 A OUTPUT SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFT) FEATURES D Qualification in Accordance With AEC-Q100(1) D Qualified for Automotive Applications D Customer-Specific Configuration Control Can Be Supported Along With Major-Change www.DataSheet4U.com Approval DESCRIPTION As members of the SWIFT family of dc/dc regulators, the TPS54310 low-input-voltage high-output-current synchronous-buck PWM converter integrates all required active components. Included on the substrate with the listed features are a true, high-performance, voltage error amplifier that provides high performance under transient conditions, an undervoltage-lockout circuit to prevent start up until the input voltage reaches 3 V, an internally and externally set slow-start circuit to limit in-rush currents, and a power good output useful for processor/logic reset, fault signaling, and supply sequencing. The TPS54310 device is available in a thermally enhanced 20-pin TSSOP (PWP) PowerPAD package, which eliminates bulky heatsinks. Texas Instruments provides evaluation modules and the SWIFT designer software tool to aid in quickly achieving high-performance power supply designs to meet aggressive equipment development cycles. D 60-mΩ MOSFET Switches for High Efficiency D D D D D D at 3-A Continuous Output Source or Sink Current 0.9-V to 3.3-V Adjustable Output Voltage With 1% Accuracy Externally Compensated for Design Flexibility Fast Transient Response Wide PWM Frequency: Fixed 350 kHz, 550 kHz, or Adjustable 280 kHz to 700 kHz Load Protected by Peak Current Limit and Thermal Shutdown Integrated Solution Reduces Board Area and Total Cost (1) Contact Texas Instruments for details. Q100 qualification data available on request. APPLICATIONS D Point of Load Regulation for High D Performance DSPs, FPGAs, ASICs, and Microprocessors Automotive Systems − Navigation Units − Entertainment Modules − Satellite Radio Industrial High-Density Systems With Power Distributed at 5 V or 3.3 V D ORDERING INFORMATION TJ OUTPUT VOLTAGE PACKAGED DEVICES PLASTIC HTSSOP (PWP)(1) −40°C to 125°C 0.9 V to 3.3 V TPS54310QPWPRQ1 (1) The PWP package is taped and reeled as indicated by the R suffix to the device type (i.e., TPS54310QPWPRQ1). See the Application section of the data sheet for PowerPAD drawing and layout information. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD and SWIFT are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2007, Texas Instruments Incorporated TPS54310 Q1 SGLS280B − JANUARY 2005 − REVISED FEBRUARY 2007 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. EFFICIENCY vs LOAD CURRENT 96 94 92 Efficiency − % 90 88 86 84 Simplified Schematic Input VIN PH BOOT PGND Output TPS54310 COMP VBIAS VSENSE AGND Compensation Network www.DataSheet4U.com 82 80 0 TA = 25°C VI = 5 V VO = 3.3 V 0.5 1 1.5 2 2.5 3 Load Current − A ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) TPS54310-Q1 VIN, SS/ENA, FSEL RT Input voltage range, VI VSENSE BOOT VBIAS, PWRGD, COMP Output voltage range, VO Source current, IO PH PH COMP, VBIAS PH Sink current Voltage differential Continuous power dissipation Operating virtual junction temperature range, TJ Storage temperature, Tstg COMP SS/ENA,PWRGD AGND to PGND −0.3 to 7 −0.3 to 6 −0.3 to 4 −0.3 to 17 −0.3 to 7 −0.6 to 10 Internally Limited 6 6 6 10 ±0.3 mA A mA mA V UNIT V V V V V V See Power Dissipation Rating Table −40 to 150 −65 to 150 °C °C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300 °C (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 www.ti.com TPS54310 Q1 SGLS280B − JANUARY 2005 − REVISED FEBRUARY 2007 RECOMMENDED OPERATING CONDITIONS MIN Input voltage range, VI Operating junction temperature, TJ 3 −40 NOM MAX 6 125 UNIT V °C PACKAGE DISSIPATION RATINGS(1) (2) PACKAGE 20-pin PWP with solder 20-pin PWP without solder THERMAL IMPEDANCE JUNCTION-TO-AMBIENT 26°C/W 57.5°C/W TA = 25°C POWER RATING 3.85 W(3) 1.73 W TA = 70°C POWER RATING 2.12 W 0.96 W TA = 85°C POWER RATING 1.54 W 0.69 W (1) For more information on the PWP package, see the Texas Instruments technical brief (SLMA002). www.DataSheet4U.com (2) Test board conditions: 1. 3” × 3”, 2 layers, Thickness: 0.062” 2. 1.5 oz copper traces located on the top of the PCB 3. 1.5 oz copper ground plane on the bottom of the PCB 4. Ten thermal vias (see the recommended land pattern in application section of this data sheet) (3) Maximum power dissipation may be limited by overcurrent protection. 3 TPS54310 Q1 SGLS280B − JANUARY 2005 − REVISED FEBRUARY 2007 www.ti.com ELECTRICAL CHARACTERISTICS TJ = −40°C to 125°C, VIN = 3 V to 6 V (unless otherwise noted) PARAMETER SUPPLY VOLTAGE, VIN VIN input voltage range fs = 350 kHz, FSEL ≤ 0.8 V, RT open, phase pin open Quiescent current fs = 550 kHz, FSEL ≥ 2.5 V, RT open, phase pin open Shutdown, SS/ENA = 0 V UNDER VOLTAGE LOCK OUT www.DataSheet4U.com Start threshold voltage, UVLO Stop threshold voltage, UVLO Hysteresis voltage, UVLO Rising and falling edge deglitch, UVLO(1) BIAS VOLTAGE VO Output voltage, VBIAS Output current, VBIAS(2) I(VBIAS) = 0 2.7 2.8 2.95 100 V µA V 2.7 2.95 2.8 0.16 2.5 3 V V µs 3 6.2 8.4 1 6 9.6 12.8 1.4 mA V TEST CONDITIONS MIN TYP MAX UNIT CUMULATIVE REFERENCE Vref Accuracy(1) REGULATION Line regulation(1) (3) Load regulation (1) (3) OSCILLATOR Internally set free-running frequency range FSEL ≤ 0.8 V, FSEL ≥ 2.5 V, RT open RT open IL = 1.5 A, fs = 350 kHz, TJ = 125°C IL = 1.5 A, fs = 550 kHz, TJ = 125°C IL = 0 A to 3 A, fs = 350 kHz, TJ = 125°C IL = 0 A to 3 A, fs = 550 kHz, TJ = 125°C 0.882 0.891 0.900 0.07 0.07 0.03 0.03 %/V %/A 265 415 252 290 663 2.5 350 550 280 312 700 440 680 308 350 762 kHz RT = 180 kΩ (1% resistor to AGND)(1) Externally set free-running frequency range High-level threshold voltage, FSEL Low-level threshold voltage, FSEL Pulse duration, FSEL(1) Frequency range, FSEL(1) (4) Ramp valley(1) Ramp amplitude (peak-to-peak)(1) Minimum controllable on time(1) Maximum duty cycle(1) RT = 160 kΩ (1% resistor to AGND) RT = 68 kΩ (1% resistor to AGND)(1) kHz V 0.8 50 330 0.75 1 200 90% 700 V ns kHz V V ns (1) Specified by design (2) Static resistive loads only (3) Specified by the circuit used in Figure 10. (4) To ensure proper operation when RC filter is used between external clock and FSEL pin, the recommended values are R ≤ 1kΩ and C ≤ 120 pF. 4 www.ti.com TPS54310 Q1 SGLS280B − JANUARY 2005 − REVISED FEBRUARY 2007 ELECTRICAL CHARACTERISTICS (continued) TJ = −40°C to 125°C, VIN = 3 V to 6 V (unless otherwise noted) PARAMETER ERROR AMPLIFIER Error amplifier open loop voltage gain Error amplifier unity gain bandwidth Error amplifier common-mode input voltage range Input bias current, VSENSE(1) Output voltage slew rate (symmetric), COMP(1) 1-kΩ COMP to AGND(1) Parallel 10 kΩ, 160 pF COMP to AGND (1) Powered by internal LDO(1) VSENSE = Vref 1 90 3 0 60 1.4 110 5 VBIAS 250 dB MHz V nA V/µs TEST CONDITIONS MIN TYP MAX UNIT IIB VO PWM COMPARATOR www.DataSheet4U.com PWM comparator propagation delay time, PWM comparator input to PH pin (excluding dead time) SLOW-START/ENABLE Enable threshold voltage, SS/ENA Enable hysteresis voltage, SS/ENA(1) Falling edge deglitch, SS/ENA(1) Internal slow-start time(1) Charge current, SS/ENA Discharge current, SS/ENA POWER GOOD Power good threshold voltage Power good hysteresis voltage(1) Power good falling edge deglitch(1) Output saturation voltage, PWRGD Leakage current, PWRGD CURRENT LIMIT Current limit trip point Current limit leading edge blanking time Current limit total response time THERMAL SHUTDOWN Thermal shutdown trip point(1) Thermal shutdown hysteresis(1) OUTPUT POWER MOSFETS rDS(on) Power MOSFET switches 10-mV overdrive(1) 70 85 ns 0.82 1.2 0.03 2.5 1.4 V V µs 2.6 SS/ENA = 0 V SS/ENA = 0.2 V, VI = 2.7 V VSENSE falling 2.5 1.2 3.35 5 2.3 4.1 8 4 ms µA mA 90 3 35 %Vref %Vref µs 0.3 1 V µA I(sink) = 2.5 mA VI = 5.5 V VI = 3 V, output shorted(1) VI = 6 V, output shorted(1) 4 4.5 0.18 6.5 7.5 100 200 A ns ns °C °C 88 136 135 150 10 165 IO = 3 A, IO = 3 A, VI = 6 V(2) VI = 3 V(2) 59 85 mΩ (1) Specified by design (2) Matched MOSFETs, low side rDS(on) production tested, high side rDS(on) specified by design 5 TPS54310 Q1 SGLS280B − JANUARY 2005 − REVISED FEBRUARY 2007 www.ti.com PIN ASSIGNMENTS PWP PACKAGE (TOP VIEW) www.DataSheet4U.com AGND VSENSE COMP PWRGD BOOT PH PH PH PH PH 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RT FSEL SS/ENA VBIAS VIN VIN VIN PGND PGND PGND Terminal Functions TERMINAL NAME AGND BOOT COMP PGND PH PWRGD RT SS/ENA FSEL NO. 1 5 3 11−13 6−10 4 20 18 19 DESCRIPTION Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor, and FSEL pin. Make PowerPAD connection

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