Description
TPS3600D20, TPS3600D25, TPS3600D33, TPS3600D50 BATTERY-BACKUP SUPERVISORS FOR LOW-POWER PROCESSORS SLVS336A – DECEMBER 2000 – REVISED APRIL 2001 features typical applications D D D D D D D D D D D D D Supply Current of 40 µA (Max) Precision Supply Voltage Monitor – 2.0 V, 2.5 V, 3.3 V, 5.0 V – Other Versions on Request Watchdog Timer With 800-ms Time-Out Backup-Battery Voltage Can Exceed VDD Power-On Reset Generator With Fixed 100-ms Reset Delay Time Battery OK Output Voltage Monitor for Power-Fail or Low-Battery Monitoring Manual Switchover to Battery-Backup Mode Chip-Enable Gating –3 ns (at VDD = 5 V) Max. Propagation Delay Manual Reset Battery Freshness Seal 14-Pin TSSOP Package Temperature Range . . . –40°C to 85°C D D D D D D D D D Fax Machines Set-Top Boxes Advanced Voice Mail Systems Portable Battery Powered Equipment Computer Equipment Advanced Modems Automotive Systems Portable Long-Time Monitoring Equipment Point of Sale Equipment TSSOP (PW) Package (TOP VIEW) VOUT VDD GND MSWITCH CEIN BATTON PFI 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VBAT RESET WDI MR CEOUT BATTOK PFO ACTUAL SIZE (5,10mm x 6,60mm) www.DataSheet4U.com typical operating circuit Power Supply 0.1 µF External Source Rx CEIN CEOUT Backup Battery Address Bus CE CMOS RAM VCC 8 16 CE CMOS RAM VCC 8 RealTime Clock VCC Address Decoder VDD VBAT TPS3600 PFI RESET WDI PFO BATTOK MR BATTON uC RESET I/O I/O I/O I/O Switchover Capacitor 0.1 µF VCC GND Data Bus Ry Manual Reset MSWITCH V OUT GND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2001, Texas Instruments Incorporated POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TPS3600D20, TPS3600D25, TPS3600D33, TPS3600D50 BATTERY-BACKUP SUPERVISORS FOR LOW-POWER PROCESSORS SLVS336A – DECEMBER 2000 – REVISED APRIL 2001 description The TPS3600 family of supervisory circuits monitor and control processor activity. In case of power-fail or brownout conditions, the backup-battery switchover function of TPS3600 allows to run a low-power processor and its peripherals from the installed backup battery without asserting a reset beforehand. During power on, RESET is asserted when the supply voltage (VDD or VBAT) becomes higher than Vres. Thereafter, the supply voltage supervisor monitors VOUT and keeps RESET output active as long as VOUT remains below the threshold voltage (VIT). An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. This delay timer starts its time-out, after VOUT has risen above the threshold voltage (VIT). In case of a brownout or power failure of both supply sources, a voltage drop below the threshold voltage (VIT) get detected and the output becomes active (low) again. The product spectrum is designed for supply voltages of 2 V, 2.5 V, 3.3 V, and 5 V. The circuits are available in a 14-pin TSSOP package. They are characterized for operation over a temperature range of –40°C to 85°C. PACKAGE INFORMATION TA DEVICE NAME TPS3600D20 40°C –40°C to 85°C TPS3600D25 TPS3600D33 TPS3600D50 ordering information application specific versions (see Note) TPS360 0 D 20 PW R Reel Package Nominal Supply Voltage Nominal BATTOK Threshold Voltage Functionality Family DEVICE NAME TPS3600x20 PW TPS3600x25 PW TPS3600x33 PW TPS3600x50 PW NOMINAL VOLTAGE, VNOM 2.0 V 2.5 V 3.3 V 5.0 V NOMINAL BATTOK DEVICE NAME TPS3600Dxx PW TPS3600Fxx PW{ TPS3600Hxx PW{ TPS3600Jxx PW{ THRESHOLD VOLTAGE, VBOK VIT + 7% VIT + 6% VIT + 8% VIT + 10% † For the application specific versions, please contact the local TI sales office for availability and lead time. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS3600D20, TPS3600D25, TPS3600D33, TPS3600D50 BATTERY-BACKUP SUPERVISORS FOR LOW-POWER PROCESSORS SLVS336A – DECEMBER 2000 – REVISED APRIL 2001 FUNCTION TABLES VDD > VSW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VOUT > VIT 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VDD > VBAT 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MSWITCH 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MR 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VOUT VBAT VBAT VBAT VBAT VDD VDD VBAT VBAT VBAT VBAT VBAT VBAT VDD VDD VBAT VBAT VDD VDD VBAT VBAT VDD VDD VBAT VBAT BATTON 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RESET 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CEOUT DIS DIS DIS DIS DIS DIS DIS DIS DIS EN DIS EN DIS EN DIS EN DIS EN DIS EN DIS EN DIS EN VBAT > VBOK 0 1 BATTOK 0 1 CONDITION: VOUT > VDD(min) CEIN 0 1 CONDITION: Enabled PFI > VPFI 0 1 PFO 0 1 CEOUT 0 1 CONDITION: VOUT > VDD(min) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TPS3600D20, TPS3600D25, TPS3600D33, TPS3600D50 BATTERY-BACKUP SUPERVISORS FOR LOW-POWER PROCESSORS SLVS336A – DECEMBER 2000 – REVISED APRIL 2001 functional schematic TPS3600 MR MSWITCH VBAT + _ VDD Switch Control VOUT Internal Supply Voltage BATTON Reference Voltage or 1.15 V R1 GND _ R2 + RESET Logic and Timer _ PFO PFI Oscillator + + _ BATTOK RESET WDI Transition Detector 40 kΩ Watchdog Logic and Control VOUT CEIN CEOUT 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS3600D20, TPS3600D25, TPS3600D33, TPS3600D50 BATTERY-BACKUP SUPERVISORS FOR LOW-POWER PROCESSORS SLVS336A – DECEMBER 2000 – REVISED APRIL 2001 timing diagram V(BOK) V(SWP) V(SWN) V(IT) VBAT VDD VOUT t V(SWN) t RESET t BATTOK 1 0 t BATTON VBAT VDD VBAT VDD VBAT t NOTES: A. MSWITCH = 0, MR = 1 NOTES: B. Timing diagram shown under normal operation, not in freshness seal mode. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TPS3600D20, TPS3600D25, TPS3600D33, TPS3600D50 BATTERY-BACKUP SUPERVISORS FOR LOW-POWER PROCESSORS SLVS336A – DECEMBER 2000 – REVISED APRIL 2001 Terminal Functions TERMINAL NAME BATTOK BATTON CEIN CEOUT GND MR MSWITCH PFI PFO RESET VBAT VDD VOUT WDI NO. 9 6 5 10 3 11 4 7 8 13 14 2 1 12 I/O O O I O I I I I O O I I O I Battery status output Logic output/external bypass switch driver output Chip-enable input Chip-enable output Ground Manual reset input Manual switch to force device into battery-backup mode (connect to GND if not used) Power-fail comparator input (connect to GND if not used) Power-fail comparator output Active-low reset output Backup-battery input Input supply voltage Supply output Watchdog timer input DESCRIPTION detailed description battery freshness seal The battery freshness seal of the TPS3600 family disconnects the backup battery from the internal circuitry until it is needed. This ensures that the backup battery connected to VBAT should be fresh when the final product is put to use. The following steps explain how to enable the freshness seal mode: 1. Connect VBAT (VBAT > VBAT(min)) 2. Ground PFO 3. Connect PFI to VDD or PFI > V(PFI) 4. Connect VDD to power supply (VDD > VIT) 5. Ground MR 6. Power down VDD 7. The freshness seal mode is entered and pins PFO and MR can be disconnected. The battery freshness seal mode is disabled by the positive-going edge of RESET when VDD is applied. BATTOK output This is a logic feedback of the device to indicate the status of the backup battery. The supervisor checks the battery voltage every 200 ms with a voltage divider load of approximately 100 KΩ and a measure cycle on-time of 25 µs. This measurement cycle starts after the reset is released. If the battery voltage VBAT is below the negative-going threshold voltage V(BOK), the indicator BATTOK does a high-to-low transition. Otherwise, its status remains to the VOUT level. Table 1. Typical Values for BATTOK Indication SUPERVISOR TYPE TPS3600D20 TPS3600D25 TPS3600D33 TPS3600D50 VIT TYP 1.78 V 2.22 V 2.93 V 4.40 V VBOK MIN 1.84 V 2.3 V 3.04 V 4.56 V VBOK TYP 1.91 V 2.38 V 3.14 V 4.71 V VBOK MAX 1.97 V 2.46 V 3.24 V 4.86 V 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS3600D20, TPS3600D25, TPS3600D33, TPS3600D50 BATTERY-BACKUP SUPERVISORS FOR LOW-POWER PROCESSORS SLVS336A – DECEMBER 2000 – REVISED APRIL 2001 detailed description (continued) IBAT 25 µs 200 ms 100 µA t Figure 1. BATTOK Timing chip-enable signal gating The internal gating of chip-enable signals (CE) prevents erroneous data from corrupting CMOS RAM during an under-voltage condition. The TPS3600 use a series transmission gate from CEIN to CEOUT. During normal operation (reset not asserted), the CE transmission gate is enabled and passes all CE transitions. When reset is asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. The short CE propagation delay from CEIN to CEOUT enables the TPS3600 devices to be used with most processors. The CE transmission gate is disabled and CEIN is high impedance (disable mode) while reset is asserted. During a power-down sequence when VDD crosses the reset threshold, the CE transmission gate will be disabled and CEIN immediately becomes high impedance if the voltage at CEIN is high. If CEIN is low during reset is asserted, the CE transmission gate will be disabled same time when CEIN goes high, or 15 µs after reset asserts, whichever occurs first. This will allow the current write cycle to complete during power down. When the CE transmission gate is enabled, the impedance of CEIN appears as a resistor in series with the load at CEOUT. The overall device propagation delay through the CE transmission gate depends on VOUT, the source impedance of the device connected to CEIN and the load at CEOUT. To achieve minimum propagation delay, the capacitive load at CEOUT should be minimized, and a low-output-impedance driver be used. During disable mode, the transmission gate is o

Part Number
TPS3600D50

Free Sample / Buy Component / Product Information
Locate Part TPS3600D50

Datasheet
Locate DataSheet

TPS3600D50 Cross Reference : Jump New Window
Get Cross-Reference Datasheet