(TMP90C400 / TMP90C401) CMOS 8-bit Microcontrollers

www.DataSheet4U.com TOSHIBA TLCS-90 Series CMOS 8–Bit Microcontrollers TMP90C400N/TMP90C401N TMP90C400F/TMP90C401F 1. Outline and Characteristics The TMP90C400 is a high-speed advanced 8-bit microcontroller applicable to a variety of equipment. With its 8-bit CPU, ROM, RAM, timer/event counter and general-purpose serial interface integrated into a single CMOS chip, the TMP90C400 allows the expansion of external memories for programs and data (up to 60K bytes). The TMP90C401 is the same as the TMP90C400 but without ROM. The TMP90C400N/401N is in a shrink Dual Inline Package (SDIP64-P-750). The TMP90C400F/401F is in a Quad Flat package (QFP64-P-1420A) The characteristics of the TMP90C400 include: (1) Powerful instructions: 163 basic instructions, including Multiplication, division, 16-bit arithmetic operations, bit manipulation instructions Minimum instruction executing time: 320ns (at 12.5MHz oscillation frequency) Internal ROM: 4K bytes (The TMP90C401 does not have a built-in ROM) (4) (5) Internal RAM: 128 bytes Memory expansion External memory: 60K bytes (6) General-purpose serial interface (1 channel) Asynchronous mode, I/O interface mode (7) 8-bit timers (4 channel): (2 external clock inputs) (8) Port with zero-cross detection circuit (4 inputs) (9) Input/Output ports (56 pins) - Ports with programmable pull-up resistor (22 pins) - Allows I/O selection on bit basis - Multiplexer ports of address data bus (10) Interrupt function: 7 internal interrupts and 3 external interrupts (11) Micro Direct Memory Access (DMA) function (8 channels) (12) Standby function (4 HALT modes) TMP90C400/401 (2) (3) The information contained here is subject to change without notice. The information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic equipments (office equipment, communication equipment, measuring equipment, domestic electrification, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equipments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traffic signal, combustion control, all types of safety devices, etc.). TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA. TOSHIBA CORPORATION 1 www.DataSheet4U.com TMP90C400/401 Figure 1. TMP90C400 Block Diagram 2 TOSHIBA CORPORATION www.DataSheet4U.com TMP90C400/401 2. Pin Assignment and Functions This section describes the assignment of input/output pins, their names and functions. 2.1 Pin Assignment Figure 2.1 (1) shows pin assignment of the TMP90C400N/ 401N. Figure 2.1 (1). Pin Assignment (Shrink Dual Inline Package) TOSHIBA CORPORATION 3 www.DataSheet4U.com TMP90C400/401 Figure 2.1 (2) shows Pin Assignment of the TMP90C400F/401F. Figure 2.1 (2). Pin Assignment (Flat Package) 4 TOSHIBA CORPORATION www.DataSheet4U.com TMP90C400/401 2.2 Pin Names and Functions The names of input/output pins and their functions are summarized in Table 2.2. Table 2.2 Pin Names and Functions (1/2) Pin Name P00 ~ P07 /AD0 ~ AD7 No. of pins 8 I/O 3 states I/O 3 states I/O Function Port 0: 8-bit I/O port that allows selection of input/output on byte basis Address/Data bus: Functions as 8-bit bidirectional address/data bus for external memory (For 401, fixed to address/data bus) Port 1: 8-bit I/O port that allows selection on byte basis Address bus: Functions as address bus (upper 8 bits) by EXT1 set for external memory (For 401, fixed to address bus Port 20 ~ 23: 4-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis Port 24: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis Non-maskable interrupt request pin: Falling edge interrupt register pin P10 ~ P17 /A8 ~ A15 P20 ~ P23 8 Output I/O I/O 4 P24 /NMI 1 Input I/O Input 1 Output Output Output Output I/O P25 /WAIT P26 /RD P27 /WR 1 Port 25: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis Wait: Input pin for connecting slow speed memory of peripheral LSI Port 26: 1-bit output port Read: Generates strobe signal for reading external memory (For 401, fixed to RD) Port 27: 1-bit output port Write: Generates strobe signal for writing into external memory (for 401, fixed to WR) Port 30: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis Interrupt request pin 0: Interrupt request pin (Level/rising edge is programmable) 1 P30 /INTO 1 Input P31 /INT1 Port 31: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis 1 Input Interrupt request pin 1: Rising edge interrupt request pin P32 /TI0 1 I/O Input Port 32: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis Timer input 0: Counter input pin for Timer 0 TOSHIBA CORPORATION 5 www.DataSheet4U.com TMP90C400/401 Table 2.2 Pin Names and Functions (2/2) Pin Name P33 /TI2 No. of pins 1 I/O 3 states I/O Input Function Port 33: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis Timer input 2: Counter input pin for Timer 2 Port 34: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis Timer input: Output of Timer 0 or 1 Port 35: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis Port 36: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis Serial clock output Port 37: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis Transmitter serial data Port 4: 8-bit I/O port that allows I/O selection on bit basis Port 5: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis Port 6: 8-bit I/O port that allows I/O selection on bit basis Address latch enable signal: The negative edge ALE supplies an address latch timing on AD0 ~ A07 for external memory External access: Connects with VCC pin in the TMP90C400 using internal ROM, and with GND pin in the TMP90C401 with no internal ROM Clock output: Generates clock pulse at 1/4 frequency of clock oscillation. It is pulled up internally during resetting. Reset: Initializes the TMP90C400/401 (Built-in pull-up resistor) Pin for quartz crystal or ceramic resonator (1 ~ 12.5MHz) Power supply (+5V) Ground (0V) P34 /T01 P35 /RxD P36 /SCLK 1 I/O Input 1 I/O I/O Output 1 P37 TxD P40 ~ P47 P50 ~ P57 P60 ~ P67 ALE EA CLK RESET X1/X2 VCC VSS 1 8 8 8 1 1 1 1 2 1 1 I/O Output I/O I/O I/O Output Input Output Input Input/Output – – 6 TOSHIBA CORPORATION www.DataSheet4U.com TMP90C400/401 3. Operation This chapter describes the functions and the basic operations of the TMP90C400/401 in every block. The following is a description of TMP90C400 which can also be applied to TMP90C401, if not specifically defined otherwise. 3.1 CPU The TMP90C400 includes a high performance 8-bit CPU. For the function of the CPU, see the book TLCS Series CPU Core Architecture concerning CPU operation. This chapter explains exclusively the functions of the CPU of TMP90C400 which are not described in th that book. 3.1.1 Reset The basic timing of the reset operation is indicated in Figure 3.1 (1). In order to reset the TMP90C400, the RESET input must be maintained at the “0” level for at least ten system clock cycles (10 stated: 2µsec at 10MHz) within an operating voltage band and with a stable oscillation. When a reset request is accepted, all I/O ports function as input ports (high impedance state). The P26 (RD), P27 (WR) and CLK pins that always function as output pins turn to the “1” level. The dedicated input ports remain unchanged. The registers of the CPU also remain unchanged. Note, however, that the program counter PC, the interrupt enable flag IFF are cleared to “0”. Register A shows an undefined status. When the reset is cleared, the CPU starts executing instructions from the address 0000H. TOSHIBA CORPORATION 7 www.DataSheet4U.com TMP90C400/401 Figure 3.1 (1a). TMP90C400 Reset Timing * P20 ~ P25, P30 ~ P37 and P50 ~ P57, which have programmable pull-up resistors, remain “High” while resetting, unless input “Low”. 8 TOSHIBA CORPORATION www.DataSheet4U.com TMP90C400/401 Figure 3.1 (1b). TMP90C401 Reset Timing 3.1.2 EXF (Exchange Flag) For TMP90C400, “EXF”, which is inverted when the command “EXX” is executed to transfer data between the main register and the auxiliary register, is allocated to the first bit of memory address FF8FH. TOSHIBA CORPORATION 9 www.DataSheet4U.com TMP90C400/401 3.1.3 Wait Control For TMP90C400, a wait control register (WAITC) is allocated to the 5th and 6th bits of memory address FF86H. 10 TOSHIBA CORPORATION www.DataSheet4U.com TMP90C400/401 3.2 Memory Map The TMP90C400 supports a program memory and a data memory of up to 60K bytes. The program and data memory may be assigned to the address space from 0000H to FFFFH. (1) Internal ROM The TMP90C400 internally contains an 4K-byte ROM. The address space from 0000H ~ 0FFFH is provided to the ROM. The CPU starts executing a program from 0000H by resetting. The addresses 0010H ~ 005FH in this intern