16/32-Bit RISC Flash Microcontroller

www.DataSheet4U.com TMS470R1B768 16/32-Bit RISC Flash Microcontroller www.ti.com SPNS108 – AUGUST 2005 FEATURES • • High-Performance Static CMOS Technology TMS470R1x 16/32-Bit RISC Core (ARM7TDM™) – 60-MHz (Pipeline Mode) – Independent 16/32-Bit Instruction Set – Open Architecture With Third-Party Support – Built-In Debug Module – Utilizes Big-Endian Format Integrated Memory – 768K-Byte Program Flash • 3 Banks With 18 Contiguous Sectors • Internal State Machine for Programming and Erase – 48K-Byte Static RAM (SRAM) 15 Dedicated GIO Pins,1 Input-Only GIO Pin, and 71 Additional Peripheral I/Os Operating Features – Core Supply Voltage (VCC ): 1.81–2.05 V – I/O Supply Voltage (VCCIO): 3.0–3.6 V – Low-Power Modes: STANDBY and HALT – Extended Industrial Temperature Range 470+ System Module – 32-Bit Address Space Decoding – Bus Supervision for Memory and Peripherals – Analog Watchdog (AWD) Timer – Real-Time Interrupt (RTI) – System Integrity and Failure Detection – Interrupt Expansion Module (IEM) Direct Memory Access (DMA) Controller – 32 Control Packets and 16 Channels Zero-Pin Phase-Locked Loop (ZPLL)-Based Clock Module With Prescaler – Multiply-by-4 or -8 Internal ZPLL Option – ZPLL Bypass Mode • • • • • • • • • • • • • • (1) Ten Communication Interfaces: – Five Serial Peripheral Interfaces (SPIs) • 255 Programmable Baud Rates – Two Serial Communications Interfaces (SCIs) • 224 Selectable Baud Rates • Asynchronous/Isosynchronous Modes – Three High-End CAN Controllers (HECCs) • 32-Mailbox Capacity Each • Fully Compliant With CAN Protocol, Version 2.0B High-End Timer (HET) – 32 Programmable I/O Channels: • 24 High-Resolution Pins • 8 Standard-Resolution Pins – High-Resolution Share Feature (XOR) – High-End Timer RAM • 128-Instruction Capacity 16-Channel 10-Bit Multi-Buffered ADC (MibADC) – 256-Word FIFO Buffer – Single- or Continuous-Conversion Modes – 1.55 µs Minimum Sample and Conversion Time – Calibration Mode and Self-Test Features Eight External Interrupts Flexible Interrupt Handling External Clock Prescale (ECP) Module – Programmable Low-Frequency External Clock (CLK) On-Chip Scan-Base Emulation Logic, IEEE Standard 1149.1(1) (JTAG) Test-Access Port 144-Pin Plastic Low-Profile Quad Flatpack (PGE Suffix) The test-access port is compatible with the IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary Scan Architecture specification. Boundary scan is not supported on this device. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. ARM7TDM is a trademark of Advanced RISC Machines Limited (ARM). All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005, Texas Instruments Incorporated TMS470R1B768 16/32-Bit RISC Flash Microcontroller SPNS108 – AUGUST 2005 www.ti.com TMS470R1B768 144-Pin PGE Package (Top View) ADIN[0] ADIN[1] ADIN[2] ADIN[3] ADIN[4] ADIN[15] ADIN[5] ADIN[6] ADIN[7] ADEVT SPI3ENA SPI3SCS SPI3SIMO SPI3SOMI SPI3CLK VCC VSS SCI1RX SCI1TX SCI1CLK CAN1HTX CAN1HRX VCC VSS GIOB[7] CLKOUT VCCIO VSSIO HET[9] HET[8] CAN3HTX CAN3HRX TCK TDO TDI PLLDIS ADIN[11] ADIN[14] ADIN[10] ADIN[13] ADIN[9] ADIN[12] ADIN[8] ADREFHI ADREFLO VCCAD VSSAD TMS TMS2 GIOC[0] HET[23] HET[25] HET[26] HET[27] VSS VCC HET[0] HET[1] VSS VCC FLTP2 FLTP1 VCCP VSS HET[2] HET[3] HET[4] HET[5] HET[6] HET[7] GIOC[1] GIOC[2] 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 AWD HET[18] HET[19] HET[20] HET[21] HET[22] SPI2SCS SPI2ENA SPI2SOMI SPI2SIMO SPI2CLK SPI5ENA SPI5CLK SPI5SOMI SPI5SIMO CAN2HRX CAN2HTX VCC VSS VCCIO VSSIO HET[24] HET[31] HET[30] HET[29] HET[28] SPI5SCS SCI2CLK SCI2TX SCI2RX GIOA[3]/INT3 GIOA[2]/INT2 GIOA[1]/INT1/ECLK GIOA[0]/INT0(A) TEST TRST A. GIOA[0]/INT0 (pin 39) is an input-only GIO pin. 2 SPI1ENA SPI1SCS SPI1SIMO SPI1SOMI SPI1CLK SPI4ENA SPI4SCS SPI4SIMO SPI4SOMI SPI4CLK VSS OSCOUT OSCIN VCC RST VSSIO VCCIO GIOD[3] GIOD[2] GIOD[1] GIOD[0] HET[17] HET[16] HET[15] HET[14] HET[13] HET[12] HET[11] HET[10] VSS VCC PORRST GIOA[7]/INT7 GIOA[6]/INT6 GIOA[5]/INT5 GIOA[4]/INT4 www.ti.com TMS470R1B768 16/32-Bit RISC Flash Microcontroller SPNS108 – AUGUST 2005 DESCRIPTION The TMS470R1B768 (1) device is a member of the Texas Instruments (TI) TMS470R1x family of general-purpose16/32-bit reduced instruction set computer (RISC) microcontrollers. The B768 microcontroller offers high performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting in a high instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-bit RISC CPU views memory as a linear collection of bytes numbered upwards from zero. The TMS470R1B768 utilizes the big-endian format where the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte. High-end embedded control applications demand more performance from their controllers while maintaining low costs. The B768 RISC core architecture offers solutions to these performance and cost demands while maintaining low power consumption. The B768 device contains the following: • ARM7TDMI 16/32-Bit RISC CPU • TMS470R1x system module (SYS) with 470+ enhancements [including an interrupt expansion module (IEM) and a 16-channel direct-memory access (DMA) controller] • 768K-byte flash • 48K-byte SRAM • Zero-pin phase-locked loop (ZPLL) clock module • Analog watchdog (AWD) timer • Real-time interrupt (RTI) module • Five serial peripheral interface (SPI) modules • Two serial communications interface (SCI) modules • Three high-end CAN controller (HECC) modules • 10-bit multi-buffered analog-to-digital converter (MibADC) with 16 input channels • High-end timer (HET) controlling 32 I/Os • External clock prescale (ECP) module • Up to 86 I/O pins and 1 input-only pin The functions performed by the 470+ system module (SYS) include: • Address decoding • Memory protection • Memory and peripherals bus supervision • Reset and abort exception management • Expanded interrupt capability with prioritization for all internal interrupt sources • Device clock control • Direct-memory access (DMA) and control • Parallel signature analysis (PSA) This data sheet includes device-specific information such as memory and peripheral select assignment, interrupt priority, and a device memory map. For a more detailed functional description of the SYS module, see the TMS470R1x System Module Reference Guide (literature number SPNU189). For a more detailed functional description of the IEM module, see the TMS470R1x Interrupt Expansion Module (IEM) Reference Guide (literature number SPNU211). And for a more detailed functional description of the DMA module, see the TMS470R1x Direct-Memory Access (DMA) Controller Reference Guide (literature number SPNU210). The B768 memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte, half-word, and word modes. The flash memory on this device is a nonvolatile, electrically erasable and programmable memory implemented with a 32-bit-wide data bus interface.The flash operates with a system clock frequency of up to 24 MHz. When in pipeline mode, the flash operates with a system clock frequency of up to 60 MHz. For more detailed information on the F05 devices flash, see the F05 flash section of this data sheet. (1) Throughout the remainder of this document, TMS470R1B768 shall be referred to as either the full device name or B768. 3 TMS470R1B768 16/32-Bit RISC Flash Microcontroller SPNS108 – AUGUST 2005 www.ti.com The B768 device has ten communication interfaces: five SPIs, two SCIs, and three HECCs. The SPI provides a convenient method of serial interaction for high-speed communications between similar shift-register type devices. The SCI is a full-duplex, serial I/O interface intended for asynchronous communication between the CPU and other peripherals using the standard Non-Return-to-Zero (NRZ) format. The HECC uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 megabit per second (Mbps). The HECC is ideal for applications operating in noisy and harsh environments (e.g., industrial fields) that require reliable serial communication or multiplexed wiring. For more detailed functional information on the SPI, SCI, and HECC, see the specific reference guides for these modules (literature numbers SPNU195, SPNU196, and SPNU197, respectively). The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. For more detailed functional information on the HET, see the TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199). T