ETHERNET TRANSCEIVERS

www.DataSheet4U.com www.ti.com TLK1201ARCP, TLK1201AIRCP ETHERNET TRANSCEIVERS SLLS580A – FEBRUARY 2004 – REVISED JUNE 2004 • • • • • • • • • 0.6-Gbps to 1.3-Gbps Serializer/Deserializer Low Power Consumption <200 mW at 1.25 Gbps LVPECL Compatible Differential I/O on High Speed Interface Single Monolithic PLL Design Support For 10-Bit Interface or Reduced Interface 5-Bit DDR (Double Data Rate) Clocking Receiver Differential Input Thresholds 200 mV Minimum IEEE 802.3 Gigabit Ethernet Compliant ANSI X3.230-1994 (FC-PH) Fibre Channel Compliant Advanced 0.25-µm CMOS Technology • • • • • • • • • No External Filter Capacitors Required Comprehensive Suite of Built-In Testability IEEE 1149.1 JTAG Support 2.5-V Supply Voltage for Lowest Power Operation 3.3-V Tolerant on LVTTL Inputs Hot Plug Protection 64-Pin VQFP With Thermally Enhanced Package (PowerPAD™) CPRI Data Rate Compatible (614 Mbps, 1.22 Gbps) Industrial Temperature Range Supported: –40°C to 85°C GNDPLL VDD TXP TXN VDDA VDDA GNDA VDDA JTRSTN JTMS RXP VDDA RXN GNDA GND TD0 TD1 TD2 VDD TD3 TD4 TD5 TD6 VDD TD7 TD8 TD9 GND MODESEL PRBSEN 1 2 3 4 5 6 7 8 9 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VDD TCK JTDI SYNC/PASS GND RD0 RD1 RD2 VDD RD3 RD4 RD5 RD6 VDD RD7 RD8 RD9 GND Copyright © 2004, Texas Instruments Incorporated 10 11 12 13 14 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DESCRIPTION The TLK1201A/TLK1201AI gigabit ethernet transceiver provides for ultrahigh-speed, full-duplex, point-to-point data transmissions. This device is based on the timing requirements of the 10-bit interface specification by the IEEE 802.3 gigabit ethernet specification and is also compliant with the ANSI X3.230-1994 (FC-PH) fibre channel standard. The device supports data rates from 0.6 Gbps to 1.3 Gbps. The primary application of the transceiver is to provide building blocks for point-to-point baseband data transmission over controlled impedance media of 50 Ω or 75 Ω. The transmission media can be printed-circuit board traces, copper cables, or fiber-optical media. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TESTEN VDDPLL LOOPEN VDD GND REFCLK VDD SYNCEN GND LOS JTDO ENABLE VDD RBC1 RBC0 RBCMODE TLK1201ARCP, TLK1201AIRCP ETHERNET TRANSCEIVERS SLLS580A – FEBRUARY 2004 – REVISED JUNE 2004 www.ti.com The transceiver performs the data serialization, deserialization, and clock extraction functions for a physical layer interface device. The transceiver operates at 1.25 Gbps (typical), providing up to 1 Gbps of data bandwidth over a copper or optical media interface. The transceiver supports both the defined 10-bit interface (TBI) and a reduced 5-bit interface utilizing double data rate (DDR) clocking. In the TBI mode the serializer/deserializer (SERDES) accepts 10-bit wide 8b/10b parallel encoded data bytes. The parallel data bytes are serialized and transmitted differentially at PECL compatible voltage levels. The SERDES extracts clock information from the input serial stream and deserializes the data, outputting a parallel 10-bit data byte. In the DDR mode the parallel interface accepts 5-bit wide 8b/10b encoded data aligned on both the rising and falling edges of the reference clock. The data is clocked most significant bit first (bits 0–4 of the 8b/10b encoded data) on the rising edge of the clock and the least significant bits (bits 5–9 of the 8b/10b encoded data) are clocked on the falling edge of the clock. The transceiver provides a comprehensive series of built-in tests for self-test purposes including loopback and pseudorandom binary sequence (PRBS) generation and verification. An IEEE 1149.1 JTAG port is also supported. The transceiver is housed in a high-performance, thermally enhanced, 64-pin VQFP PowerPAD package. Use of the PowerPAD package does not require any special considerations except to note that the PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. It is recommended that the device PowerPAD be soldered to the thermal land on the board. The transceiver is characterized for operation from 0°C to 70°C (TLK1201A) or –40°C to 85°C (TLK1201AI). The transceiver uses a 2.5-V supply. The I/O section is 3.3-V compatible. With a 2.5-V supply the chipset is very power-efficient, dissipating less than 200 mW typical power when operating at 1.25 Gbps. The transceiver is designed to be hot plug capable. A power-on reset causes RBC0, RBC1, the parallel output signal terminals, TXP, and TXN to be held in a high-impedance state. Differences Between TLK1201A/TLK1201AI and TNETE2201 The TLK1201A/TLK1201AI transceiver is the functional equivalent of the TNETE2201. There are several differences between the devices as noted below. See Figure 12 in the Application Information section for an example of a typical application circuit. • The VCC is 2.5 V for the TLK1201A vs 3.3 V for TNETE2201. • The PLL filter capacitors on terminals 16, 17, 48, and 49 of the TNETE2201 are no longer required. The TLK1201A uses these terminals to provide added test capabilities. The capacitors, if present, do not affect the operation of the device. • No pulldown resistors are required on the TXP/TXN outputs. AVAILABLE OPTIONS TA 0°C to 70°C –40°C to 85°C PACKAGE PLASTIC QUAD FLAT PACK (RCP) TLK1201ARCP TLK1201AIRCP 2 www.ti.com TLK1201ARCP, TLK1201AIRCP ETHERNET TRANSCEIVERS SLLS580A – FEBRUARY 2004 – REVISED JUNE 2004 BLOCK DIAGRAM PRBSEN LOOPEN PRBS Generator 10 Bit Registers Clock REFCLK MODESEL ENABLE TESTEN RBC1 RBC0 SYNC/PASS Control Logic Phase Generator TXP 2:1 MUX Parallel to Serial TXN TD(0-9) PRBS Verification Interpolator and Clock Extraction Clock 2:1 MUX Clock RD(0-9) Serial to Parallel and Comma Detect 2:1 MUX Data RXP RXN SYNCEN RBCMODE JTMS JTRSTN JTDI TCK JTAG Control Register JTDO LOS Terminal Functions TERMINAL NAME SIGNAL MODESEL 15 I P/D (1) O Mode select. This terminal selects between the 10-bit interface and a reduced 5-bit DDR interface. When low, the 10-bit interface (TBI) is selected. When pulled high, the 5-bit DDR mode is selected. The default mode is the TBI. Loss of signal. Indicates a loss of signal on the high-speed differential inputs RXP and RXN. If the magnitude of RXP-RXN > 150 mV, then LOS = 1 which is a valid input signal. If the magnitude of RXP-RXN > 50 mV and < 150 mV, then LOS is undefined. If the magnitude of RXP-RXN < 50 mV, then LOS = 0 which is a loss of signal. Receive clock mode select. When RBCMODE and MODESEL are low, half-rate clocks are output on RBC0 and RBC1. When MODESEL is low and RBCMODE is high, a full baud-rate clock is output on RBC0 and RBC1 is held low. When MODESEL is high, RBCMODE is ignored and a full baud-rate clock is output on RBC0 and RBC1 is held low. Receive byte clock. RBC0 and RBC1 are recovered clocks used for synchronizing the 10-bit output data on RD0–RD9. The operation of these clocks is dependent upon the receive clock mode selected. In the half-rate mode, the 10-bit output data words are valid on the rising edges of RBC0 and RBC1. These clocks are adjusted to half-word boundaries in conjunction with synchronous detect. The clocks are always expanded during data realignment and never slivered or truncated. RBC0 registers bytes 1 and 3 of received data. RBC1 registers bytes 0 and 2 of received data. In the normal rate mode, only RBC0 is valid and operates at 1/10th the serial data rate. Data is aligned to the rising edge. In the DDR mode, only RBC0 is valid and operates at 1/10th the serial data rate. Data is aligned on both the rising and falling edges. NO. I/O DESCRIPTION LOS 26 RBCMODE 32 I P/D (1) RBC0 RBC1 31 30 O (1) P/D = Internal pulldown 3 TLK1201ARCP, TLK1201AIRCP ETHERNET TRANSCEIVERS SLLS580A – FEBRUARY 2004 – REVISED JUNE 2004 www.ti.com Terminal Functions (continued) TERMINAL NAME RD0–RD9 NO. 45, 44, 43, 41, 40, 39, 38, 36, 35, 34 22 I/O O DESCRIPTION Receive data. When in TBI mode (MODESEL = low), these outputs carry 10-bit parallel data output from the transceiver to the protocol layer. The data is referenced to terminals RBC0 and RBC1, depending on the receive clock mode selected. RD0 is the first bit received.When in the DDR mode (MODESEL = high), only RD0–RD4 are valid. RD5–RD9 are held low. The 5-bit parallel data is clocked out of the transceiver on the rising edge of RBC0. Reference clock. REFCLK is an external input clock that synchronizes the receiver and transmitter interface (60 MHz to 130 MHz). The transmitter uses this clock to register the input data (TD0–TD9) for serialization.In the TBI mode that data is registered on the rising edge of REFCLK. In the DDR mode, the data is registered on both the rising and falling edges of REFCLK with the most significant bits aligned on the rising edge of REFCLK. Differential input receive. RXP and RXN together are the differential serial input interface from a copper or an optical I/F module. Synchronous function enable. When SYNCEN is high, the internal synchronization function is activated. When this function is activated, the transceiver detects the K28.5 comma character (0011111 negative beginning disparity) in the serial data stream and realigns data on byte boundaries if required. When SYNCEN is low, serial input data is unframed in RD0–RD9. Synchronous detect. The SYNC output is asserted high upon detection of the comma pattern in the serial data path. SYNC pulses are output only when SYNCEN is activated