HIGH PERFORMANCE PHASE LOCKED LOOP

TLC2933A HIGH PERFORMANCE PHASE LOCKED LOOP SLES149 − OCTOBER 2005 D VCO (Voltage-Controlled Oscillator): − Complete Oscillator Using Only One External Bias Resistor (RBIAS) − Lock Frequency: 30 MHz to 55 MHz (VDD = 3 V +5%, TA = –205C to 755C, x1 Output) 30 MHz to 60 MHz (VDD = 3.3 V +5%, TA = –205C to 755C, x1 Output) 43 MHz to 110 MHz (VDD = 5 V +5%, TA = –205C to 755C, x1 Output) − Selectable Output Frequency D PFD (Phase Frequency Detector): High Speed, Edge-Triggered Detector with Internal Charge Pump D D D D Independent VCO, PFD Power-Down Mode Thin Small-Outline Package (14 Terminal) CMOS Technology Pin Compatible TLC2933IPW 14-PIN TSOP (PW PACKAGE) (TOP VIEW) LOGIC VDD SELECT VCO OUT FIN −A FIN −B PFD OUT LOGIC GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCO VDD RBIAS VCO IN VCO GND VCO INHIBIT PFD INHIBIT TEST description The TLC2933A is designed for phase-locked loop (PLL) systems and is composed of a voltage-controlled oscillator (VCO) and an edge-triggered type phase frequency detector (PFD). The oscillation frequency range of the VCO is set by an external bias resistor (RBIAS). The VCO has a 1/2 frequency divider at the output stage. The high speed PFD with internal charge pump detects the phase difference between the reference frequency input and signal frequency input from the external counter. Both the VCO and the PFD have inhibit functions, which can be used as power-down mode. Due to the TLC2933A high speed and stable oscillation capability, the TLC2933A is suitable for use as a high-performance PLL. www.DataSheet4U.com AVAILABLE OPTIONS PACKAGE TA –20°C to 75°C SMALL OUTLINE (PW) TLC2933AIPW Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Copyright  2005, Texas Instruments Incorporated TI.COM 1 TLC2933A HIGH PERFORMANCE PHASE LOCKED LOOP SLES149 − OCTOBER 2005 functional block diagram 4 5 9 Phase Frequency Detector 6 PFD OUT VCO INHIBIT SELECT VCO IN BIAS 12 13 10 2 Voltage Controlled Oscillator 3 FIN−A FIN−B PFD INHIBIT VCO OUT Terminal Functions TERMINAL NAME LOGIC VDD SELECT VCO OUT FIN−A FIN−B PFD OUT LOGIC GND TEST PFD INHIBIT VCO INHIBIT VCO GND VCO IN RBIAS VCO VDD NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 I I I I I O I I O I/O DESCRIPTION Power supply for the internal logic. This power supply should be separated from VCO VDD to reduce cross-coupling between supplies. VCO output frequency select. When SELECT is high, the VCO output frequency is ×1/2 and when low. The output frequency is ×1. VCO output. When the VCO INHIBIT is high, VCO output is low. Input reference frequency f(REF IN) is applied to FIN−A. Input for VCO external counter output frequency f(FIN−B). FIN−B is nominally provided from the external counter. PFD output. When the PFD INHIBIT is high, PFD output is in the high-impedance state. GND for the internal logic. Connect to GND. PFD inhibit control. When PFD INHIBIT is high, PFD output is in the high-impedance state. VCO inhibit control. When VCO INHIBIT is high, VCO output is low. GND for VCO. VCO control voltage input. Nominally the external loop filter output connects to VCO IN to control VCO oscillation frequency. Bias supply. An external resistor (RBIAS) between VCO VDD and RBIAS supplies bias for adjusting the oscillation frequency range. Power supply for VCO. This power supply should be separated from LOGIC VDD to reduce cross-coupling between supplies. 2 TI.COM TLC2933A HIGH PERFORMANCE PHASE LOCKED LOOP SLES149 − OCTOBER 2005 detailed description VCO oscillation frequency The VCO oscillation frequency is determined by an external register (RBIAS) connected between the VCO VDD and the BIAS terminals. The oscillation frequency and range depends on this Resistor value. For the lock frequency range, refer to the recommended operating conditions. Figure 1 shows the typical frequency variation and VCO control voltage. VCO Oscillation Frequency − fOSC VCO Oscillation Frequency Range Bias Resistor (RBIAS) 1/2 VDD VCO Control Voltage (VCO IN) Figure 1. Oscillation Frequency VCO output frequency 1/2 divider The TLC2933A SELECT terminal sets the fOSC VCO output frequency as shown in Table 1. The 1/2 fOSC output should be used for minimum VCO output jitter. Table 1. VCO Output 1/2 Divider Function SELLECT Low High VCO OUTPUT fOSC 1/2 fOSC VCO inhibit function The VCO has an externally controlled inhibit function which inhibit the VCO output. A high level on the VCO INHIBIT terminal stops the VCO oscillation and powers down the VCO. The output maintains a low level during the power−down mode as shown in Table 2. Table 2. VCO Inhibit Function VCO INHIBIT Low High VCO OSCILLATOR Active Stopped VCO OUT Active Low level IDD(VCO) Normal Power Down PFD operation The PFD is a high-speed, edge-triggered detector with an internal charge pump. The PFD detects the phase difference between two frequency inputs supplied to FIN−A and FIN−B as shown in Figure 2. Normally the reference is supplied to FIN−A and the frequency from the external counter output is fed to FIN−B. For clock recovery PLL system, other types of phase detectors should be used. TI.COM 3 TLC2933A HIGH PERFORMANCE PHASE LOCKED LOOP SLES149 − OCTOBER 2005 FIN−A FIN−B VOH PFD OUT HI-Z VOL Figure 2. PFD Function Timing Chart PFD inhibit control A high level on the PFD INHIBIT terminal places PFD OUT in the high-impedance state and the PFD stops phase detection as shown in Table 3. A high level on the PFD INHIBIT terminal can also be used as the power-down mode for the PFD. Table 3. VCO Output Control Function PFD INHIBIT Low High DETECTION Active Stopped PFD OUT Active Hi−Z IDD(PFD) Normal Power Down VCO block schematic PFD block schematic Charge Pump VDD FIN−A PFD OUT Detector FIN−B PFD INHIBIT 4 TI.COM TLC2933A HIGH PERFORMANCE PHASE LOCKED LOOP SLES149 − OCTOBER 2005 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage (each supply), VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage range (each input), VIN (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VDD + 0.5 V Input current (each input), IIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output current (each output), IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20°C to 75°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to GND. 2. For operation above 25_C free-air temperature, derate linearly at the rate of 5.6 mW/°C. recommended operating conditions PARAMETERS VDD = 3 V Supply voltage (each supply, see Note 3) Input voltage, (inputs except VCO IN) Output current, (each output) VCO control voltage at VCO IN Lock frequency VDD = 3 V VDD = 3.3 V VDD = 5 V VDD = 3 V Bias resisitor VDD = 3.3 V VDD = 5 V MIN 2.85 3.135 4.75 0 0 0.9 30 30 43 2.2 TYP 3 3.3 5 MAX 3.15 3.465 5.25 VDD ±2 VDD 55 60 110 5.1 V mA V MHz UNIT V VDD = 3.3 V 2.2 5.1 kΩ VDD = 5 V 2.2 5.1 NOTE 3: It is recommended that the logic supply terminal (LOGIC VDD) and the VCO supply terminal (VCO VDD) should be at the same voltage and separated from each other. electrical characteristics, VDD = 3 V, TA = 25°C (unless otherwise noted) VCO section PARAMETER VOH VOL VTH II ZI(VCO IN) IDD(INH) High level output voltage Low level output voltage Input threshold voltage at select, VCO inhibit Input current at Select, VCO inhibit VCO IN input impedance VCO supply current (inhibit) VI = VDD or GND VCO IN = 1/2 VDD See Note 4 TEST CONDITIONS IOH = –2 mA IOL = 2 mA MIN 2.4 0.3 0.9 1.5 10 0.41 1 2.1 ±1 TYP MAX UNIT V V V µA MΩ µA mA IDD(VCO) VCO supply current See Note 5 11.7 23 NOTES: 4. Current into VCO VDD, when VCO INHIBIT = high, PFD is inhibited. 5. Current into VCO VDD, when VCO IN = 1/2 VDD, RBIAS = 3.3 kΩ, VCOOUT = 15-pF Load, VCO INHIBIT = GND, and PFD INHIBIT = GND. TI.COM 5 TLC2933A HIGH PERFORMANCE PHASE LOCKED LOOP SLES149 − OCTOBER 2005 electrical characteristics, VDD = 3 V, TA = 25°C (unless otherwise noted) (continued) PFD section PARAMETER VOH VOL IOZ VIH VIL VTH CIN ZIN IDD(Z) High level output voltage Low level output voltage High impedance state output current High level input voltage at Fin−A, Fin−B Low level input voltage at Fin−A, Fin−B Input threshold voltage at PFD inhibit Input capacitance at Fin−A, Fin−B Input impedance at Fin−A, Fin−B High impedance state PFD supply current See Note 6 0.9 1.5 5.6 10 1 TEST CONDITIONS IOH = –2 mA IOL = 2 mA PFD inhibit = high, VO = VDD or GND 2.1 0.5 2.1 pF MΩ µA MIN 2.4 0.3 ±1 TYP MAX UNIT V V µA V V IDD(PFD) PFD supply current See Note 7 3 mA NOTES: 6. The current into LOGIC VDD when