DUAL UART

TL16C2552 www.ti.com SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006 1.8-V to 5-V DUAL UART WITH 16-BYTE FIFOS FEATURES • • • • Programmable Auto-RTS and Auto-CTS In Auto-CTS Mode, CTS Controls the Transmitter In Auto-RTS Mode, RCV FIFO Contents, and Threshold Control RTS Serial and Modem Control Outputs Drive a RJ11 Cable Directly When Equipment is on the Same Power Drop Capable of Running With All Existing TL16C450 Software After Reset, All Registers Are Identical to the TL16C450 Register Set Up to 24-MHz Clock Rate for up to 1.5-Mbaud Operation With VCC = 5 V Up to 20-MHz Clock Rate for up to 1.25-Mbaud Operation With VCC = 3.3 V Up to 16-MHz Clock Rate for up to 1-Mbaud Operation With VCC = 2.5 V Up to 10-MHz Clock Rate for up to 625-kbaud Operation With VCC = 1.8 V In the TL16C450 Mode, Hold and Shift Registers Eliminate the Need for Precise Synchronization Between the CPU and Serial Data Programmable Baud Rate Generator Allows Division of Any Input Reference Clock by 1 to (216 - 1) and Generates an Internal 16 × Clock Standard Asynchronous Communication Bits (Start, Stop, and Parity) Added to or Deleted From the Serial Data Stream 5-V, 3.3-V, 2.5-V, and 1.8 V Operation Independent Receiver Clock Input Transmit, Receive, Line Status, and Data Set Interrupts Independently Controlled Fully Programmable Serial Interface Characteristics: – 5-, 6-, 7-, or 8-Bit Characters – Even-, Odd-, or No-Parity Bit Generation and Detection – 1-, 1 ½-, or 2-Stop Bit Generation – Baud Generation (dc to 1 Mbit/s) • • • • • False-Start Bit Detection Complete Status Reporting Capabilities 3-State Output TTL Drive Capabilities for Bidirectional Data Bus and Control Bus Line Break Generation and Detection Internal Diagnostic Capabilities: – Loopback Controls for Communications Link Fault Isolation – Break, Parity, Overrun, and Framing Error Simulation Fully Prioritized Interrupt System Controls Modem Control Functions (CTS, RTS, DSR, DTR, RI, and DCD) Available in 44-Pin PLCC (FN) or 32-Pin QFN (RHB) Packages Each UART's Internal Register Set May Be Written Concurrently to Save Setup Time Multi-Function Output (MF) Allows Users to Select Among Several Functions, Saving Package Pins • • • • • www.DataSheet4U.com • • • • • • • APPLICATIONS • • • • • • Point-of-Sale Terminals Gaming Terminals Portable Applications Router Control Cellular Data Factory Automation • • DESCRIPTION The TL16C2552 is a dual universal asynchronous receiver and transmitter (UART). It incorporates the functionality of two TL16C550D UARTs, each UART having its own register set and FIFOs. The two UARTs share only the data bus interface and clock source, otherwise they operate independently. Another name for the UART function is Asynchronous Communications Element (ACE), and these terms will be used interchangeably. The bulk of this document describes the behavior of each ACE, with the understanding that two such devices are incorporated into the TL16C2552. • • • • Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2006, Texas Instruments Incorporated TL16C2552 www.ti.com SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006 Each ACE is a speed and voltage range upgrade of the TL16C550C, which in turn is a functional upgrade of the TL16C450. Functionally equivalent to the TL16C450 on power up or reset (single character or TL16C450 mode), each ACE can be placed in an alternate FIFO mode. This relieves the CPU of excessive software overhead by buffering received and to be transmitted characters. Each receiver and transmitter store up to 16 bytes in their respective FIFOs, with the receive FIFO including three additional bits per byte for error status. In the FIFO mode, a selectable autoflow control feature can significantly reduce software overload and increase system efficiency by automatically controlling serial data flow using handshakes between the RTS output and CTS input, thus eliminating overruns in the receive FIFO. Each ACE performs serial-to-parallel conversions on data received from a peripheral device or modem and stores the parallel data in its receive buffer or FIFO, and each ACE performs parallel-to-serial conversions on data sent from its CPU after storing the parallel data in its transmit buffer or FIFO. The CPU can read the status of either ACE at any time. Each ACE includes complete modem control capability and a processor interrupt system that can be tailored to the application. Each ACE includes a programmable baud rate generator capable of dividing a reference clock with divisors of from 1 to 65535, thus producing a 16× internal reference clock for the transmitter and receiver logic. Each ACE accommodates up to a 1.5-Mbaud serial data rate (24-MHz input clock). As a reference point, that speed would generate a 667-ns bit time and a 6.7-µs character time (for 8,N,1 serial data), with the internal clock running at 24 MHz. Each ACE has a TXRDY and RXRDY output that can be used to interface to a DMA controller. FN PACKAGE (TOP VIEW) TXRDYA DSRA CTSA VCC 6 5 D3 4 D2 3 D1 2 1 44 43 42 41 40 D5 D6 D7 A0 XTAL1 GND XTAL2 A1 A2 CHSEL INTB RIA CDA D4 D0 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 RXA TXA DTRA RTSA MFA INTA VCC TXRDYB RIB CDB DSRB TL16C2552FN 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 MFB RESET DTRB CTSB RTSB IOW GND RXB TXB CS IOR RHB PACKAGE (TOP VIEW) 32 31 30 29 28 27 26 D6 D7 A0 XTAL1 XTAL2 A1 A2 CHSEL 25 CTSA VCC D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 24 23 22 RXA TXA RTSA INTA GND NC NC CTSB TL16C2552RHB 21 20 19 18 17 10 12 13 14 15 IOW INTB IOR RESET RXB CS NC − No internal connection NOTE: The 32-pin RHB package does not provide access to DSRA, DSRB, RIA, RIB, CDA, CDB inputs and MFA, MFB, DTRA, DTRB, TXRDYA, TXRDYB outputs. 2 Submit Documentation Feedback RTSB TXB 16 9 11 TL16C2552 www.ti.com SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006 TL16C2552 Block Diagram UART Channel A A2 − A0 D7 − D0 CS CHSEL IOR IOW INTA INTB TXRDYA TXRDYB MFA MFB RESET BAUD Rate Gen UART Regs 16 Byte Tx FIFO Tx Data Bus Interface UART Channel B TXB CTSB DTRB DSRB, RIB, CDB RTSB 16 Byte Rx FIFO Rx RXB BAUD Rate Gen UART Regs 16 Byte Tx FIFO Tx TXA CTSA DTRA DSRA, RIA, CDA RTSA 16 Byte Rx FIFO Rx RXA XTAL1 XTAL2 Crystal OSC Buffer VCC GND A. MF output allows selection of OP, BAUDOUT, or RXRDY per channel. DEVICE INFORMATION TERMINAL FUNCTIONS TERMINAL NAME A0 A1 A2 CDA, CDB FN NO. 10 14 15 42, 30 RHB NO. 3 6 7 – I/O I I I I DESCRIPTION Address 0 select bit. Internal registers address selection Address 1 select bit. Internal registers address selection Address 2 select bit. Internal registers address selection Carrier detect (active low). These inputs are associated with individual UART channels A and B. A low on these pins indicates that a carrier has been detected by the modem for that channel. The state of these inputs is reflected in the modem status register (MSR). Channel select. UART channel A or B is selected by the state of this pin when CS is a logic 0. A logic 0 on the CHSEL selects the UART channel B while a logic 1 selects UART channel A. CHSEL could just be an address line from the user CPU such as A3. Bit 0 of the alternate function register (AFR) can temporarily override CHSEL function, allowing the user to write to both channel register simultaneously with one write cycle when CS is low. It is especially useful during the initialization routine. UART chip select (active low). This pin selects channel A or B in accordance with the state of the CHSEL pin. This allows data to be transferred between the user CPU and the 2552. Clear to send (active low). These inputs are associated with individual UART channels A and B. A logic low on the CTS pins indicates the modem or data set is ready to accept transmit data from the 2552. Status can be tested by reading MSR bit 4. These pins only affect the transmit and receive operations when auto CTS function is enabled through the enhanced feature register (EFR) bit 7, for hardware flow control operation. CHSEL 16 8 I CS 18 10 I CTSA, CTSB 40, 28 25, 17 I Submit Documentation Feedback 3 TL16C2552 www.ti.com SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006 DEVICE INFORMATION (continued) TERMINAL FUNCTIONS (continued) TERMINAL NAME D0-D4 D5-D7 DSRA, DSRB FN NO. 2-6 7-9 RHB NO. 27 - 31 32, 1, 2 I/O I/O DESCRIPTION Data bus (bidirectional). These pins are the eight bit, 3-state data bus for transferring information to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data stream. Data set ready (active low). These inputs are associated with individual UART channels A and B. A logic low on these pins indicates the modem or data set is powered on and is ready for data exchange with the UART. The state of these inputs is reflected in the modem status register (MSR). Data terminal ready (active low). These outputs are associated with individual UART channels A and B. A logic low on these pins indicates that theTLl16C2552 is powered on and ready. These pins can be controlled through the modem control register. Writing a 1 to MCR bit 0 sets the DTR output to low, enabling the modem. The output of these pins is high after writing a 0 to MCR bit 0, or after a reset. Signal and power ground. Interrupt A and B (active high). These pins provide individual channel interrupts, INT A and B. INT A and B are enabled when MCR bit 3 is set t