DUAL UART

TL16C2550 www.ti.com SLWS161 – JUNE 2005 2.5-V to 5-V DUAL UART WITH 16-BYTE FIFOS FEATURES • • • • Programmable Auto-RTS and Auto-CTS In Auto-CTS Mode, CTS Controls Transmitter In Auto-RTS Mode, RCV FIFO Contents and Threshold Control RTS Serial and Modem Control Outputs Drive a RJ11 Cable Directly When Equipment Is on the Same Power Drop Capable of Running With All Existing TL16C450 Software After Reset, All Registers Are Identical to the TL16C450 Register Set Up to 24-MHz Clock Rate for up to 1.5-Mbaud Operation With VCC = 5 V Up to 20-MHz Clock Rate for up to 1.25-Mbaud Operation With VCC = 3.3 V Up to 16-MHz Clock Rate for up to 1-Mbaud Operation With VCC = 2.5 V In the TL16C450 Mode, Hold and Shift Registers Eliminate the Need for Precise Synchronization Between the CPU and Serial Data Programmable Baud Rate Generator Allows Division of Any Input Reference Clock by 1 to (216 - 1) and Generates an Internal 16 × Clock Standard Asynchronous Communication Bits (Start, Stop, and Parity) Added to or Deleted From the Serial Data Stream 5-V, 3.3-V, and 2.5-V Operation Independent Receiver Clock Input Transmit, Receive, Line Status, and Data Set Interrupts Independently Controlled Fully Programmable Serial Interface Characteristics: – 5-, 6-, 7-, or 8-Bit Characters – Even-, Odd-, or No-Parity Bit Generation and Detection – 1-, 1 1/2-, or 2-Stop Bit Generation – Baud Generation (dc to 1 Mbit/s) False-Start Bit Detection Complete Status Reporting Capabilities 3-State Output TTL Drive Capabilities for Bidirectional Data Bus and Control Bus Line Break Generation and Detection • Internal Diagnostic Capabilities: – Loopback Controls for Communications Link Fault Isolation – Break, Parity, Overrun, and Framing Error Simulation Fully Prioritized Interrupt System Controls Modem Control Functions (CTS, RTS, DSR, DTR, RI, and DCD) Available in 48-Pin TQFP (PFB), 44-Pin PLCC (FN), or 32-Pin QFN (RHB) Packages Pin Compatible with TL16C752B (48-Pin Package) • • • • • • • • • • www.DataSheet4U.com APPLICATIONS DESCRIPTION The TL16C2550 is a dual universal asynchronous receiver and transmitter (UART). It incorporates the functionality of two TL16C550D UARTs, each UART having its own register set and FIFOs. The two UARTs share only the data bus interface and clock source, otherwise they operate independently. Another name for the uart function is Asynchronous Communications Element (ACE), and these terms will be used interchangeably. The bulk of this document will describe the behavior of each ACE, with the understanding that two such devices are incorporated into the TL16C2550. • • • • • • • • • • Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Copyright © 2005, Texas Instruments Incorporated PRODUCT PREVIEW • • • • • • Point-of-Sale Terminals Gaming Terminals Portable Applications Router Control Cellular Data Factory Automation TL16C2550 www.ti.com SLWS161 – JUNE 2005 Each ACE is a speed and voltage range upgrade of the TL16C550C, which in turn is a functional upgrade of the TL16C450. Functionally equivalent to the TL16C450 on power up or reset (single character or TL16C450 mode), each ACE can be placed in an alternate FIFO mode. This relieves the CPU of excessive software overhead by buffering received and to be transmitted characters. Each receiver and transmitter store up to 16 bytes in their respective FIFOs, with the receive FIFO including three additional bits per byte for error status. In the FIFO mode, a selectable autoflow control feature can significantly reduce software overload and increase system efficiency by automatically controlling serial data flow using handshakes between the RTS# output and CTS# input, thus eliminating overruns in the receive FIFO. Each ACE performs serial-to-parallel conversions on data received from a peripheral device or modem and stores the parallel data in its receive buffer or FIFO, and each ACE performs parallel-to-serial conversions on data sent from its CPU after storing the parallel data in its transmit buffer or FIFO. The CPU can read the status of either ACE at any time. Each ACE includes complete modem control capability and a processor interrupt system that can be tailored to the application. Each ACE includes a programmable baud rate generator capable of dividing a reference clock with divisors of from 1 to 65535, thus producing a 16× internal reference clock for the transmitter and receiver logic. Each ACE accommodates up to a 1.5-Mbaud serial data rate (24-MHz input clock). As a reference point, that speed would generate a 667-ns bit time and a 6.7-µs character time (for 8,N,1 serial data), with the internal clock running at 24 MHz. Each ACE has a TXRDY# and RXRDY# output that can be used to interface to a DMA controller. PFB PACKAGE (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 D4 D3 D2 D1 D0 TXRDYA VCC RA CDA DSRA CTSA NC D5 D6 D7 RXB RXA TXRDYB TXA TXB OPB CSA CSB NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 TL16C2550PFB RESET DTRB DTRA RTSA OPA RXRDYA INTA INTB A0 A1 A2 NC NC −No internal connection FN PACKAGE (TOP VIEW) TXRDYA DSRA CTSA D3 D2 6 5 4 3 D1 2 1 44 43 42 41 40 D5 D6 D7 RXB RXA TXRDYB TXA TXB OPB CSA CSB CDA VCC RIA D4 D0 XTAL1 XTAL2 IOW CDB GND RXRDYB IOR DSRB RIB RTSB CTSB NC 39 38 37 36 35 XTAL1 XTAL2 RXRDYB DSRB 2 CTSB RTSB IOW CDB GND IOR RIB PRODUCT PREVIEW 7 8 9 10 11 12 13 14 15 16 17 RESET DTRB DTRA RTSA OPA RXRDYA INTA INTB A0 A1 A2 TL16C2550FN 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 TL16C2550 www.ti.com SLWS161 – JUNE 2005 RHB PACKAGE (TOP VIEW) 32 31 30 29 28 27 26 D6 D7 RXB RXA TXA TXB CSA CSB 25 CTSA VCC D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 24 23 22 RESET RTSA INTA INTB A0 A1 A2 NC TL16C2550RHB 21 20 19 18 17 10 12 13 14 15 IOW GND IOR NC XTAL1 XTAL2 CTSB RTSB 16 9 11 NC − No internal connection NOTE: The 32-pin RHB package does not provide access to DSRA, DRRB, RIA, RIB, CDA, CDB inputs, and OPA, OPB, RXRDYA, RXRDYB, TXRDYA, TXRDYB outputs. UART Channel A A2 − A0 D7 − D0 CSA CSB IOR IOW INTA INTB TXRDYA TXRDYB RXRDYA RXRDYB RESET BAUD Rate Gen UART Regs 16 Byte Tx FIFO Tx Data Bus Interface UART Channel B TXB CTSB OPB, DTRB DSRB, RIB, CDB RTSB 16 Byte Rx FIFO Rx RXB BAUD Rate Gen UART Regs 16 Byte Tx FIFO Tx TXA CTSA OPA, DTRA DSRA, RIA, CDA RTSA 16 Byte Rx FIFO Rx RXA XTAL1 XTAL2 Crystal OSC Buffer VCC GND Figure 1. TL16C2550 Block Diagram 3 PRODUCT PREVIEW TL16C2550 www.ti.com SLWS161 – JUNE 2005 DEVICE INFORMATION TERMINAL FUNCTIONS TERMINAL NAME A0 A1 A2 CDA, CDB PFB NO. 28 27 26 40, 16 FN NO. 31 30 29 42, 21 RHB NO. 20 19 18 – I/O I I I I DESCRIPTION Address 0 select bit. Internal registers address selection Address 1 select bit. Internal registers address selection Address 2 select bit. Internal registers address selection Carrier detect (active low). These inputs are associated with individual UART channels A and B. A low on these pins indicates that a carrier has been detected by the modem for that channel. The state of these inputs is reflected in the modem status register (MSR). Chip select A and B (active low). These pins enable data transfers between the user CPU and the TL16C2550 for the channel(s) addressed. Individual UART sections (A, B) are addressed by providing a low on the respective CSA and CSB pins. Clear to send (active low). These inputs are associated with individual UART channels A and B. A logic low on the CTS pins indicates the modem or data set is ready to accept transmit data from the 2550. Status can be tested by reading MSR bit 4. These pins only affect the transmit and receive operations when auto CTS function is enabled through the enhanced feature register (EFR) bit 7, for hardware flow control operation. Data bus (bidirectional). These pins are the eight bit, 3-state data bus for transferring information to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data stream. Data set ready (active low). These inputs are associated with individual UART channels A and B. A logic low on these pins indicates the modem or data set is powered on and is ready for data exchange with the UART. The state of these inputs is reflected in the modem status register (MSR). Data terminal ready (active low). These outputs are associated with individual UART channels A and B. A logic low on these pins indicates that theTLl16C2550 is powered on and ready. These pins can be controlled through the modem control register. Writing a 1 to MCR bit 0 sets the DTR output to low, enabling the modem. The output of these pins is high after writing a 0 to MCR bit 0, or after a reset. Signal and power ground. Interrupt A and B (active high). These pins provide individual channel interrupts, INT A and B. INT A and B are enabled when MCR bit 3 is set to a logic 1, interrupt sources are enabled in the interrupt enable register (IER). Interrupt conditions include: receiver errors, available receiver buffer data, available transmit buffer space or when a modem status flag is detected. INTA-B are in the high-impedance state after reset. Read input (active low strobe). A high to low transition on IOR will load the contents of an internal register defined by address bits A0-A2 onto the TL16C2550 data bus (D0-D7) for access by an external CPU. Write input (active low strobe). A low to high transition on