PCI BUS INTERFACE

www.DataSheet4U.com TI380PCIA PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS™ SPWS035 – JUNE 1997 D D D D D D D D Glueless Interface Between the Peripheral Component Interconnect (PCI) Bus and the TI380C2x† and TI380C3x† Generation of Processors Compliant With PCI Specification, Revision 2.0‡§ Allows Use of Existing TI2000 Drivers Includes TI2000 Interface Configuration Register Supports Bus Master Operations for High Performance Provides 32-Bit Address-Data Path Implements Address / Data Parity Checking Includes Internal Error Checking for Illegal Bus Operations D D D D D D D Supports Direct Memory Access (DMA) Bursts With 64-Byte FIFO Supports EPROM Interface for Remote Program Load (RPL) Operation Supports Inter-Integrated Circuit (I2C) Interface for Optional Serial EEPROM for Configuration Information Allows Burned-In Address (BIA) to be Implemented in Configuration EEPROM Includes NAND Tree Structure to Allow for In-Circuit Connectivity Testing 144-Pin JEDEC Plastic Quad Flat Package (PCM Suffix) Operating Temperature Range 0_ C to 70_ C The TI380PCIA provides a glueless interface between a TI380C2x† commprocessor and the PCI bus (see Figure 1). The TI380PCIA transfers information / data between the PCI bus and the TI380C2x† system interface (SIF ) using any of these three methods: D Direct memory access (DMA) D Direct input / output (DIO) D Pseudo-direct memory access (PDMA) DMA (or PDMA) transfers all data between host memory (by way of the PCI local bus) and TI380C2x† local memory. DIO accesses are typically used to load software into TI380C2x† local memory and for initializing the TI380C2x†. The TI380PCIA conforms to the PCI standards found in “PCI Local Bus Specification,” Revision 2.0.‡§ The TI380PCIA is available in a 144-pin JEDEC plastic quad flat package (PCM suffix) and is rated from 0_ C to 70_ C. It is a drop-in replacement for the TI380PCI. EEPROM PacketBlaster™ Frame-Processing Accelerator (FPA) SIF PCI Bus TI380PCIA TI380C2x† DRAM RPL ROM Physical Layer To Network Figure 1. TI380PCIA Applications Diagram Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. † TI380C3x devices can be used with TI380PCIA in the same way as TI380C2x devices. ‡ The “PCI Local Bus Specification”, Revision 2.0, and the TI380C2x or TI380C3x series of data sheets (e.g., literature number SPWS012) should be used as references to this document. § Exceptions to electrical timing parameters specified in PCI Specification Revision 2.0 are described in Note 8 and Note 10 of the timing requirements section of this document. PacketBlaster and Commprocessor are trademarks of Texas Instruments Incorporated. ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. Copyright © 1997, Texas Instruments Incorporated POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1 ADVANCE INFORMATION description www.DataSheet4U.com TI380PCIA PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS™ pin assignments The pin assignments for the TI380PCIA (144-pin plastic quad flat package) are shown below. PCM PACKAGE ( TOP VIEW ) SXAL SALE VDD SBCLK SADL7/ROMD0 SADL6/ROMD1 SADL5/ROMD2 SADL4/ROMD3 GND SADL3/ROMD4 SADL2/ROMD5 SADL1/ROMD6 SADL0/ROMD7 MBCLK1 VDD SBRQ SRNW SDBEN SOWN SDTACK GND SUDS EDC SADH7/ROMA15 SADH6/ROMA14 SADH5/ROMA13 VDD SADH4/ROMA12 SADH3/ROMA11 SADH2/ROMA10 SADH1/ROMA09 SADH0/ROMA08 GND EDIO ICT ROMA00 120 119 115 114 113 112 111 118 117 116 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 110 SPWS035 – JUNE 1997 SLDS SAS SHALT GND SBGR SIRQ SBERR MROMEN MAX0 VDD SBRLS SCS SRSX SRS0 SRS1 GND SRESET MAX2 MBIAEN INTA RST VDD PCLK GND GNT REQ AD31 GND AD30 AD29 GND AD28 AD27 VDD AD26 AD25 109 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 ROMA01 ROMA02 VDD ROMA03 ROMA04 ROMA05 ROMA06 ROMA07 GND MADH00 MADH01 MADH02 MADH03 MADH04 VDD MADH05 MADH06 MADH07 ROMCS DB9 / UTP GND AD00 AD01 AD02 AD03 AD04 VDD AD05 AD06 VDD AD07 C / BE0 GND AD08 AD09 AD10 ADVANCE INFORMATION NOTE: Pin 1 is positioned at the upper left corner. 2 VDD AD24 C/BE3 GND IDSEL AD23 AD22 AD21 AD20 VDD AD19 AD18 AD17 VDD AD16 GND C/BE2 GND FRAME IRDY TRDY VDD DEVSEL STOP PERR SERR PAR GND C/BE1 AD15 GND AD14 AD13 VDD AD12 AD11 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 www.DataSheet4U.com TI380PCIA PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS™ SPWS035 – JUNE 1997 block diagram TI380PCIA can connect to up to four devices in a system: the PCI bus, the SIF bus, an optional serial EEPROM, and an optional boot ROM. The major blocks of the TI380PCIA include the PCI Interface (PCIIF ), SIF, and ROM Interface (ROMIF ) as shown in Figure 2. ICT DB9 / UTP MBCLK1 MADH00 –0 7 MBIAEN Local Memory Bus Check Burned-In Address Emulation Interface (BIF) MAX2 MAX0 MROMEN AD31 – AD00 C/BE3 – C/BE0 DEVSEL FRAME GNT IDSEL INTA IRDY PAR PCLK RST REQ PERR SERR STOP TRDY PCI Interface (PCIIF) Controls Communication Between TI380PCIA and PCI Bus 64-Byte FIFO System Interface (SIF) Controls Communication Between TI380C2x† and the TI380PCIA SADH0 – SADH7 SADL0 – SADL7 SDTACK SBRLS SBRQ SHALT SDBEN SALE SXAL SOWN SBCLK SUDS SLDS SIRQ SBGR SBERR SAS SRESET SRS0 – SRS1 SRSX SCS I2C Serial EEPROM Interface (EIF) ROM Interface (ROMIF) ROMA08 – ROMA15 ROMA00 – ROMA07 ROMCS EDIO EDC † TI380C3x devices can be used with TI380PCIA in the same way as TI380C2x devices. Figure 2. TI380PCIA Block Diagram POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 3 ADVANCE INFORMATION SRNW www.DataSheet4U.com TI380PCIA PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS™ SPWS035 – JUNE 1997 Terminal Functions TERMINAL NAME NO. I/O† DESCRIPTION Connector. The value on DB9 / UTP indicates the type of connector in use. Upon reset, the DB9 / UTP value is 0. 1 = D-Shell (DB9) 0 = UTP / 10BaseT DB9 / UTP 89 O GND ADVANCE INFORMATION 4 16 24 28 31 40 52 54 64 67 76 88 100 112 124 136 I Ground. These pins must be attached to the common system ground plane. ICT supports in-circuit tests. ICT must be pulled high for normal operation of the TI380PCIA. ICT 110 I When pulled along with RST to a steady low state, all bidirectional signals in the TI380PCIA are configured as inputs, and all output pins of the TI380PCIA are in 3-state mode. ROM address. ROMA07 – ROMA00 form the least significant eight bits of the address for the RPL ROM. The most significant bits (MSBs) of the ROM address are multiplexed onto the SADHx lines. When RST is driven high, the value on ROMA07 – ROMA00 is latched into the board configuration register in the TI380PCIA configuration space. The value on ROMA07 – ROMA00 can be provided by pullup and pulldown resistors that do not affect operation after reset. This feature allows designers to support jumpers or board stuffing options that can be sensed by software that reads the board configuration register. If pullup and pulldown resistors are not used, the contents of the board configuration register are undefined after reset. ROMCS enables the outputs of the ROM when the ROM has been accessed. ROMCS-enable allows the data lines from the ROM to be driven. ROMA07 ROMA06 ROMA05 ROMA04 ROMA03 ROMA02 ROMA01 ROMA00 ROMCS 101 102 103 104 105 107 108 109 90 I/O O † I = in, O = out ‡ The TI380PCIA SIF pin names correspond to a subset of the system interface pins on a TI380C2x§. See the TI380C2x§ data sheets for more information on individual pins. Like-named pins on the TI380PCIA and TI380C2x§ system interfaces are intended to be connected to each other. § TI380C3x devices can be used with TI380PCIA in the same way as TI380C2x devices. ¶ Typical bit-ordering for Intel™ and Motorola™ processor buses # The signal connecting this pin to the TI380C2x§ also should be connected to a 4.7-kΩ pullup resistor. || The TI380PCIA BIF pin names correspond to a subset of the local memory bus interface pins on a TI380C2x§. Like-named pins on the two devices are intended to be connected to each other. Consult the TI380C2x§ data sheets for more information on individual pins. NOTE 1: The TI380PCIA allows driver software to set SBCLK output to a steady high state. This signal is driven to a steady high state during power-down operations. Intel is a trademark of Intel Incorporated. Motorola is a trademark of Motorola, Inc. 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 www.DataSheet4U.com TI380PCIA PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS™ SPWS035 – JUNE 1997 Terminal Functions (Continued) TERMINAL NAME NO. 10 22 34 37 46 50 58 70 79 82 94 106 118 130 142 I/O† DESCRIPTION VDD I 5 - V supply. These pins must be attached to the common system power supply plane. SADH0 /ROMA08 SADH1 /ROMA09 SADH2 /ROMA10 SADH3 /ROMA11 SADH4 /ROMA12 SADH5 /ROMA13 SADH6 /ROMA14 SADH7 /ROMA15 SADL0 /ROMD7 SADL1 /ROMD6 SADL2 /ROMD5 SADL3 /ROMD4 SADL4 /ROMD3 SADL5 /ROMD2 SADL6 /ROMD1 SADL7 /ROMD0 SALE 113 114 115 116 117 119 120 121 132 133 134 135 137 138 139 140 143 System address / data bus — high byte. These lines make up the most significant byte (MSByte) of each TI380C2x§ address word (32-bit address bus) and data word (16-bit data bus). The most significant bit (MSB) is SADH0, and the least significant bit (LSB) is SADH7. I/O Address-multiplexing bits 31 – 24 and bits 15 – 8¶ Data-multiplexing bits 15 – 8¶ During accesses to the R