DUAL-PROTOCOL COMMPROCESSOR

www.DataSheet4U.com TI380C27 DUAL-PROTOCOL COMMPROCESSOR SPWS014A – APRIL 1994 – REVISED MARCH 1995 • • • • IEEE 802.5 and IBM Token-Ring Network ™ Compatible IEEE 802.3 and Blue Book Ethernet ™ Network Compatible Compatible With TI380FPA FNL PacketBlaster™ Token-Ring Features – 16- or 4-Megabit-per-Second Data Rates – Supports Up to 18K-Byte Frame Size (16-Mbps Operation Only) – Supports Universal and Local Network Addressing – Early Token-Release Option (16-Mbps Operation Only) – Compatible With the TMS38054 Ethernet Features – 10 Megabit-per-Second Data Rate in Half-Duplex Mode – 20 Megabit-per-Second Data Rate in Full-Duplex Mode – Compatible With Most Ethernet Serial-Network-Interface Devices – Network-Speed Self-Test Feature Glueless Interface to DRAMs High-Performance 16-Bit CPU for Communications-Protocol Processing 1- to 16.5-Megabyte-per-Second High-Speed Bus Master DMA Interface Low-Cost Host-Slave I/O Interface Option Up to 32-Bit Host Address Bus Selectable Host System-Bus Options • • Adapter Local-Bus Speed Is Switchable Between 4 MHz and 6 MHz 80x8x or 68xxx-Type Bus and Memory Organization – 8 - or 16-Bit Data Bus on 80x8x Buses – Optional Parity Checking Dual-Port DMA and Direct I/O Transfers to Host Bus Supports 8 - or 16-Bit Pseudo-DMA Operation Enhanced-Address-Copy-Option (EACO) Interface Supports External Address-Checking Logic for Bridging or External Custom Applications • • • • • • • • • • • • • • • Built-In Real-Time Error Detection Bring-Up and Self-Test Diagnostics With Loopback Automatic Frame-Buffer Management 2- to 33-MHz System-Bus Clock Slow-Clock Low-Power Mode Single 5-V Supply 0.8 -µm CMOS Technology 250-mA Typical Latch-Up Immunity at 25°C ESD Protection Exceeds 2 000 V 144-Pin Plastic Thin Quad Flat Package (PGE Suffix) Operating Temperature Range 0°C to 70°C • • • • • • LAN Subsystem Attached System Bus (2 MHz to 33 MHz) Transmit To Network Receive TI380C27 Token-Ring or Ethernet Physical-Layer Circuitry Memory Figure 1. Network-Commprocessor Applications Diagram IBM and Token-Ring Network are trademarks of International Business Machines Corporation. PacketBlaster is a trademark of Texas Instruments Incorporated. Ethernet is a trademark of Xerox Corporation. ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. Copyright © 1995, Texas Instruments Incorporated POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1 ADVANCE INFORMATION • Support for Module High-Impedance In-Circuit Testing www.DataSheet4U.com TI380C27 DUAL-PROTOCOL COMMPROCESSOR SPWS014A – APRIL 1994 – REVISED MARCH 1995 pin assignments PGE PACKAGE ( TOP VIEW ) V SSC MRAS MW MCAS MAX2 MAX0 MDDIR VDD SYNCIN OSCIN VSS MROMEN MACS MAL MREF VSSL VSSL MBIAEN VDDL MRESET MBCLK2 MBCLK1 OSCOUT RCVR / RXD RCLK / RXC NSELOUT1 PXTALIN / TXC VSSC WRAP / TXEN DRVR DRVR WFLT/COLL NSRT / LPBK FRAQ / TXD REDY/CRS NC NC VSSL MOE MBEN MADH7 MADH6 MADH5 MADH4 VDD NC VSS MADH3 MADH2 MADH1 MADH0 MAXPH MBRQ MBGR VSS MAXPL MADL7 MADL6 MADL5 MADL4 MADL3 MADL2 MADL1 MADL0 EXTINT3 EXTINT2 EXTINT1 EXTINT0 NMI VDD NC VSSL 112 111 110 109 120 119 118 117 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 116 115 114 113 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 VSSL NC VDD XMATCH XFAIL TEST0 TEST1 TEST2 TEST3 TEST4 TEST5 SADH0 SADH1 SADH2 SADH3 SADH4 SADH5 VSSD NC VDD NC VSSC SADH6 SADH7 SPH SRD / SUDS SRDY / SDTACK SOWN SDBEN SBHE / SRNW SHRQ / SBRQ SPL SADL0 SADL1 SADL2 VSSL 2 VDDL CLKDIV VSSC NSELOUT0 PRTYEN BTSTRP SIACK SRESET SRS1 SRS0 SRSX SCS SBRLS SBBSY S8 / SHALT VSSL VSSL SRS2 / SBERR VDDL SI / M SINTR / SIRQ SHLDA / SBGR SDDIR SRAS / SAS SWR / SLDS VSS SXAL SALE SBCLK SADL7 SADL6 SADL5 SADL4 SADL3 NC VDD POST OFFICE BOX 1443 ADVANCE INFORMATION • HOUSTON, TEXAS 77251–1443 www.DataSheet4U.com TI380C27 DUAL-PROTOCOL COMMPROCESSOR SPWS014A – APRIL 1994 – REVISED MARCH 1995 description The TI380C27 is a single-chip network-communications processor (commprocessor) that supports token-ring or Ethernet local area networks (LANs). Token ring at a data rate of either 16 Mbps or 4 Mbps or Ethernet at a data rate of either 10 Mbps (half duplex) or 20 Mbps (full duplex) can be selected. A flexible configuration scheme allows network type and speed to be configured by hardware or software. This allows the design of LAN subsystems that support both token-ring and Ethernet networks by electrically or physically switched network front-end circuits. In addition, the TI380C27 can be used with the TI380FPA PacketBlaster for maximum performance. The TI380C27 token-ring capability conforms to ISO 8802 – 5 / IEEE 802.5 – 1992 standards and has been verified to be completely IBM Token-Ring Network compatible. By integrating the essential control building blocks needed on a LAN-subsystem card into one device, the TI380C27 can ensure that this IBM compatibility is maintained in silicon. The TI380C27 Ethernet capability conforms to ISO / IEC 8802 – 3 (ANSI / IEEE Std. 802.3 ) CSMA / CD standards and the Ethernet Blue Book standard. The TI380C27 provides a 32-bit system-memory address reach with a high-speed bus-master DMA interface that supports rapid communications with the host system. In addition, the TI380C27 supports direct I/O and a low-cost 8- or 16-bit pseudo-DMA interface that requires only a chip select to work directly on an 80x8x 8-bit slave I/O interface. Finally, selectable 80x8x or 68xxx-type host-system bus and memory organization add to design flexibility. The TI380C27 supports addressing for up to 2M bytes of local memory. This expanded memory capacity can improve LAN-subsystem performance by minimizing the frequency of host LAN-subsystem communications by allowing larger blocks of information to be transferred at one time. The support of large local memory is important in applications that require large data transfers (such as graphics or data-base transfers) and in heavily loaded networks where the extra memory can provide data buffers to store data until it can be processed by the host. The proprietary CPU used in the TI380C27 allows protocol software to be downloaded into RAM or stored in ROM in the local-memory space. By moving protocols to the LAN subsystem, overall system performance is increased. This is accomplished by the offloading of processing from the host system to the TI380C27, which can also reduce LAN-subsystem-to-host communications. As other protocol software is developed, greater differentiation of end products with enhanced system performance will be possible. In addition, the TI380C27 includes hardware counters that provide real-time error detection and automatic frame-buffer management. These counters control system-bus retries, control burst size, and track host and LAN-subsystem buffer status. Previously, these counters needed to be maintained in software. By integrating them into hardware, software overhead is removed and LAN-subsystem performance is improved. The TI380C27 implements a TI-patented enhanced-address-copy-option (EACO) interface. This interface supports external address-checking devices, such as the TMS380SRA source-routing accelerator. The TI380C27 has a 128-word external I/O space in its memory to support external address-checker devices and other hardware extensions to the TMS380 architecture. The major blocks of the TI380C27 include the communications processor (CP), the system interface (SIF), the memory interface (MIF), the protocol handler (PH), the clock generator (CG), and the adapter-support function (ASF), as shown in the functional block diagram. The TI380C27 is available in a 144-pin plastic thin quad flat package (PGE suffix) and is characterized for operation from 0°C to 70°C. PAL ® is a registered trademark of Advanced Micro Devices, Inc. Other companies also manufacture programmable array logic devices. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 3 ADVANCE INFORMATION The high degree of integration of the TI380C27 makes it a virtual LAN subsystem on a single chip. Protocol handling, host-system interfacing, memory interfacing, and communications processing are all provided through the TI380C27. To complete LAN-subsystem design, only the network-interface hardware, local memory, and minimal additional components such as PAL ® devices and crystal oscillators need to be added. www.DataSheet4U.com TI380C27 DUAL-PROTOCOL COMMPROCESSOR SPWS014A – APRIL 1994 – REVISED MARCH 1995 description (continued) The TI380C27 has a bus interface to the host system, a bus interface to local memory, and an interface to the physical-layer circuitry. Pin names starting with the letter S attach to the host-system bus and pin names starting with the letter M attach to the local-memory bus. Active-low signals have names with overbars; e.g., SCS. functional block diagram SADH0 SADH7 SADL0 SADL7 SPH SPL SBRLS SINTR/SIRQ SDDIR SDBEN SALE SXAL SOWN SIACK SBCLK SRD/SUDS SWR/SLDS SRDY/SDTACK SI/M SHLDA/SBGR SBHE/SRNW SRAS/SAS S8/SHALT SRESET SRS0 SRS1 SRS2/SBERR SCS SRSX SHRQ/SBRQ SBBSY BTSTRP PRTYEN NSELOUT0 NSELOUT1 System Interface (SIF) Memory Interface (MIF) MADH0 MADH7 MADL0 MADL7 MRAS MCAS MAXPH MAXPL MW MOE MDDIR MAL MAX0 MAX2 MRESET MROMEN MBEN MBRQ MBGR MACS MBIAEN MREF OSCIN OSCOUT MBCLK1 MBCLK2 SYNCIN CLKDIV NMI EXTINT0 EXTINT3 TEST0 TEST5 XMATCH XFAIL • DIO Control • Bus Control • DMA Control • DRAM Refresh • Local-Bus Arbitrator • Local-Bus Control • Local P