TGA8652-EPU-SL (TriQuint Semiconductor) - 9.9-12.5Gb/s Optical Modulator Driver (TGA8652-EPU-SL.pdf)

TriQuint Semiconductor

Description
Product Data Sheet June 14, 2005 9.9-12.5Gb/s Optical Modulator Driver OC-192 Metro and Long Haul Applications Surface Mount Package TGA8652-EPU-SL Key Features and Performance • • • • • • • • DC - 12 GHz Linear BW DC - 16 GHz Saturated Power BW 16 dB small signal gain Wide Drive Range (4V to 8V) 25 ps Edge Rates (10/90) Low Power Dissipation (1.4W at Vo=8V) Package size: .350 x .350 x .084 inches. Evaluation Board Available. www.DataSheet4U.com Primary Applications • • Mach-Zehnder Modulator Driver Pre-Driver Receiver AGC Description The TriQuint TGA8652-EPU is a medium power wideband AGC amplifier combined with off chip circuitry assembled in a Surface Mount Package. The TGA8652-EPU typically provides 16dB small signal gain with 6dB AGC range. Typical input and output return loss is <10dB. Typical Noise Figure is 2.5dB at 3GHz. Typical saturated output power is 25dBm. Small signal 3dB BW is 12GHz with saturated power performance to 16GHz. RF ports are DC coupled enabling the user to customize system corner frequencies. Applications include OC192 12.5GBit/s NRZ MZ Modulator Driver and receive AGC amplifier. Drain bias may be applied thru the on-chip drain termination resistor for low drive applications or thru the RF output port for high drive applications. A cascaded pair demonstrated 8Vpp output voltage swing with 500mVpp at the input when stimulated with 10GBit/s. 2^31-1prbs. NRZ data. The TGA8652-EPU is available on an evaluation board. • Measured Performance Cascaded 8652 Evaluation Boards 12.5 Gb/s Performance Output = 8 Vpp, Input = 500 mVpp Scale: 2 V/div, 20 ps/div Note: Devices designated as EPU are typically early in their characterization process prior to finalizing all electrical and process specifications. Specifications are subject to change without notice. 1 TriQuint Semiconductor Texas: (972)994 8465 Fax (972)994 8504 Email: info-mmw@tqs.com Web: www.triquint.com Product Data Sheet June 14, 2005 MAXIMUM RATINGS SYMBOL V + PARAMETER 1/ POSITIVE SUPPLY VOLTAGE Drain bias applied thru on-chip termination Drain bias applied at RF output using bias T POSITIVE SUPPLY CURRENT VALUE 12 V 10 V NOTES Vd(RFout) + www.DataSheet4U.com V Drain bias applied thru on-chip termination Drain bias applied at RF output using bias T POWER DISSIPATION NEGATIVE GATE Voltage Gate Current CONTROL GATE Voltage Gate Current RF INPUT Sinusoidal Continuous Wave Power OPERATING CHANNEL TEMPERATURE STORAGE TEMPERATURE 110 mA 250 mA 2.4 W 0 V to –3 V 5 mA Vd/2 to –3 V 5 mA 23 dBm 150 C -40 to 125 C 0 0 2/ Id Pd Vg Ig Vctrl Ictrl PIN TCH TSTG 3/ 4/ 5/ 6/ Notes: 1/ These ratings represent the maximum operable values for the device. 2/ Assure the combination of Vd and Id does not exceed maximum power dissipation rating. 3/ When operated at this bias condition with a base plate temperature of 80 0C, the Mean Time to Failure (MTTF) is reduced from 2.6E+7 to 1E+6 hours. 4/ Assure Vctrl never exceeds Vd during bias on and off sequences, and normal operation. 5/ These ratings apply to each individual FET. 6/ Junction operating temperature will directly affect the device median time to failure (MTTF). For maximum life, it is recommended that junction temperatures be maintained at the lowest possible levels. Note: Devices designated as EPU are typically early in their characterization process prior to finalizing all electrical and process specifications. Specifications are subject to change without notice. 2 TriQuint Semiconductor Texas: (972)994 8465 Fax (972)994 8504 Email: info-mmw@tqs.com Web: www.triquint.com Product Data Sheet June 14, 2005 THERMAL INFORMATION* Parameter Test Condition T CH (°C) 114.70 RθJC (°C/W) 31.40 MTTF (HRS) 2.6E+7 RθJC Thermal Resistance (channel to backside of package) Vd(RF out) = 6.5 V, Vctrl = 1 V, Id = 170 mA ± 5%, T base = 80 °C NOTE: Thermal transfer is conducted thru the bottom of the TGA8652-EPU package into the motherboard. Design the motherboard to assure adequate thermal transfer to the base plate. An array www.DataSheet4U.comthermal vias is recommended as shown in the example below. of filled * This information is a result of a thermal model. Thermal vias in motherboard Area of thermal transfer Motherboard Bottom View TGA8652-EPU Note: Devices designated as EPU are typically early in their characterization process prior to finalizing all electrical and process specifications. Specifications are subject to change without notice. 3 TriQuint Semiconductor Texas: (972)994 8465 Fax (972)994 8504 Email: info-mmw@tqs.com Web: www.triquint.com Product Data Sheet June 14, 2005 RF SPECIFICATIONS (TA = 25°C Nominal) NOTE TEST SMALL SIGNAL BW SATURATED POWER BW SMALL-SIGNAL GAIN MAGNITUDE www.DataSheet4U.com 1/, 2/ 2 and 4 GHz 6 GHz 10 GHz 14 GHz 16 GHz SMALL SIGNAL AGC RANGE 1/, 2/ 1/, 2/ 6/, 7/ 3/, 4/ INPUT RETURN LOSS MAGNITUDE OUTPUT RETURN LOSS MAGNITUDE SATURATED OUTPUT POWER EYE AMPLITUDE Midband 2, 4, 6, and 10 GHz 14 and 18 GHz 2, 4, 6, and 10 GHz 14 and 18 GHz 2, 4, 6, 8, and 10 GHz Vd (RFout) = 7 V Vd (RFout) = 6 V Vd (RFout) = 5 V Vd (RFout) = 4.5 V 3/, 4/, 5/ ADDITIVE JITTER (p-p) 3/, 4/ RISE TIME (10/90) 9 8 10 8 25 8.0 7.0 6.0 5.5 5 25 ps ps Vpp 15 13 13 10 10 MEASUREMENT CONDITIONS VALUE MIN TYP 12 16 16 15 14 13 13 15 10 10 10 10 dBm dB dB dB dB MAX GHz GHz UNITS Notes: 1/ Verified at package level RF probe. 2/ Package Probe Bias: V+ = 8 V, adjust Vg1 to achieve Id = 87 mA, Vctrl = +1 V 3/ Verified by design, TGA8652EPU assembled onto a demonstration board shown on page 7 then tested using the application circuit and bias procedure detailed on pages 8 and 9. 4/ Vin = 2 V, Data Rate = 12.5 Gb/s, Vctrl and Vg are adjusted for maximum output. 5/ Computed using RSS Method where Jpp_additive = SQRT(Jpp_out2 - Jpp_in2) 6/ Verified at die level on-wafer probe. 7/ Power Bias Die Probe: VDT=8 V, adjust Vg to achieve Id = 175 mA+/-5%, Vctrl = 1.5 V Note: At the die level, drain bias is applied thru the RF output port using a bias tee, voltage is at the DC input to the bias tee. Note: Devices designated as EPU are typically early in their characterization process prior to finalizing all electrical and process specifications. Specifications are subject to change without notice. 4 TriQuint Semiconductor Texas: (972)994 8465 Fax (972)994 8504 Email: info-mmw@tqs.com Web: www.triquint.com Product Data Sheet June 14, 2005 Typical Measured S-parameters 20 18 16 14 Gain (dB) 12 10 GAIN www.DataSheet4U.com 8 6 4 2 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Frequency (GHz) 0 -5 IRL Retur n Los s (dB) -10 -15 -20 -25 -30 -35 0 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 16 Frequency (GHz) Note: Devices designated as EPU are typically early in their characterization process prior to finalizing all electrical and process specifications. Specifications are subject to change without notice. 5 ORL TriQuint Semiconductor Texas: (972)994 8465 Fax (972)994 8504 Email: info-mmw@tqs.com Web: www.triquint.com Product Data Sheet June 14, 2005 Demonstration Board Vctrl www.DataSheet4U.com V+ RF(in) RF(out) Vg Note: Devices designated as EPU are typically early in their characterization process prior to finalizing all electrical and process specifications. Specifications are subject to change without notice. 6 TriQuint Semiconductor Texas: (972)994 8465 Fax (972)994 8504 Email: info-mmw@tqs.com Web: www.triquint.com Product Data Sheet June 14, 2005 Application Circuit for 4-8V Driver Application V+ (No Connection) C3 C4 www.DataSheet4U.com VDT 11 C5 Vctrl 9 Vd(RFout) 6 Bias Tee (PSPL 5542) TGA8652 RF(in) DC Block (PSPL 5509) RF(out) 12 3 Vg C1 C2 Recommended Components: DESIGNATOR C1, C3 C2, C4 C5 DESCRIPTION 1uF Capacitor MLC Ceramic 10 uF Capacitor MLC Ceramic 0.01 uF Capacitor MLC MANUFACTURER AVX AVX AVX PART NUMBER 0603YC105KAT 0603YC106KAT 0603YC103KAT Note: Devices designated as EPU are typically early in their characterization process prior to finalizing all electrical and process specifications. Specifications are subject to change without notice. 7 TriQuint Semiconductor Texas: (972)994 8465 Fax (972)994 8504 Email: info-mmw@tqs.com Web: www.triquint.com Product Data Sheet June 14, 2005 Bias Procedure for 4-8V Driver Application Bias ON www.DataSheet4U.com 1. Disable Bias OFF 1. Disable the output of the PPG 2. Set Vctrl = 0V 3. Set Vdt = 0V 4. Set Vg = 0V the PPG source 2. Set Vdt = 0V Vctrl = 0V and Vg = 0V 3. Set Vg =-1.5 V 4. Increase Vdt to 8V observing Id. - Assure Id = 0mA 5. Set Vctrl = +1.0 V - Id should still be 0 mA 6. Make Vg more positive until Idd = 175mA. - Typical value for Vg is -0.3 V 7. Enable the PPG source - Vin = 2 Vpp 8. Adjust Vctrl for Vo = 8Vpp 9. Adjust Vg for 50% crossover Notes: 1. Assure Vctrl never exceeds Vd during Bias ON and Bias OFF sequences and during normal operation. Note: Devices designated as EPU are typically early in their characterization process prior to finalizing all electrical and process specifications. Specifications are subject to change without notice. 8 TriQuint Semiconductor Texas: (972)994 8465 Fax (972)994 8504 Email: info-mmw@tqs.com Web: www.triquint.com Product Data Sheet June 14, 2005 Typical Measured Performance on Demonstration Board 12.5Gb/s 2^31-1, Vd(RFout) = 7 V CPC = 50% Vo=8 V Vo=7 V www.DataSheet4U.com Vo=6 V Vo=5 V Vo = 4 V Note: Devices designated as EPU are typically early in their characterization process prior to finalizing all electrical and process specifications. Specifications are subject to change without notice. 9 TriQuint Semiconductor Texas: (972)994 8465 Fax (972)994 8504 Email: info-mmw@tqs.com Web: www.triquint.com Product Data Sheet June 14, 2005 Typical Bias Conditions Vd(RFout) = 7 V Vo(V) 8 7 www.DataSheet4U.com Vg(V) -0.23 -0.31 -0.40 -0.48 -0.54 Id(mA) 194 173 144 117 97 Vctrl 0.87 0.63 0.37 0.16 0.02 6 5 4 Notes: 1. Vd(RFout)=7 V 2. Vin =2 Vpp 3. 50% CPC 4. Actual bias points may be different. Note:

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