40 Msps analog-to-digital interface for CCD cameras

www.DataSheet4U.com INTEGRATED CIRCUITS DATA SHEET TDA9965A 12-bit, 5.0 V, 40 Msps analog-to-digital interface for CCD cameras Product specification Supersedes data of 2003 Nov 26 2004 Jul 05 www.DataSheet4U.com Philips Semiconductors Product specification 12-bit, 5.0 V, 40 Msps analog-to-digital interface for CCD cameras FEATURES • Clamp and Track/Hold (CTH) circuit with adjustable bandwidth, Programmable Gain Amplifier (PGA), 12-bit Analog-to-Digital Converter (ADC) and reference regulator • Fully programmable via a 3-wire serial interface • Sampling frequency up to 40 MHz • PGA gain from 0 to 36 dB (in 0.05 dB steps) • CTH programmable bandwidth from 35 to 284 MHz typical • Standby mode (20 mW typical) • Low power consumption of only 425 mW typical • 5 V operation and 3 to 5.25 V operation for the digital outputs QUICK REFERENCE DATA SYMBOL VCCA VCCD VCCO ICCA ICCD ICCO ADCres Vi(IN)(p-p) GCTH PGAdyn fpix(max) Ntot(rms) Vn(i)(eq)(rms) Ptot Note 1. Noise and clamp behaviour are not guaranteed for a PGA gain higher than 30 dB. ORDERING INFORMATION TYPE NUMBER TDA9965AHL 2004 Jul 05 PACKAGE NAME LQFP48 DESCRIPTION PARAMETER analog supply voltage digital supply voltage digital output supply voltage analog supply current digital supply current digital output supply current ADC resolution CTH input voltage (peak-to-peak value) CTH output amplifier gain PGA dynamic range maximum pixel frequency total noise from CTH input to ADC output (RMS value) equivalent input noise (RMS value) total power consumption code fco(CTH) = 0000 GPGA = 0 dB; code fco(CTH) = 0000 GPGA = 30 dB; code fco(CTH) = 0000; note 1 with internal regulator with internal regulator fpix = 40 MHz; CL = 10 pF on all data outputs; ramp input CONDITIONS MIN. 4.75 4.75 3.0 − − − − − − − 40 − − − TDA9965A • TTL compatible inputs; TTL and CMOS compatible outputs. APPLICATIONS • CCD camera systems. GENERAL DESCRIPTION The TDA9965A is a 12-bit analog-to-digital interface for a CCD camera. The device includes a CTH circuit, PGA and a low-power 12-bit ADC, together with its reference voltage regulator. The CTH has a bandwidth circuit controlled by on-chip DACs via a serial interface. A 10-bit digital clamp controls the ADC input clamp level. TYP. 5.0 5.0 3.3 65 19 1 12 2 0 36 − 0.85 90 425 MAX. 5.25 5.25 5.25 − − − − − − − − − − − UNIT V V V mA mA mA bits V dB dB MHz LSB µV mW VERSION SOT313-2 plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm 2 www.DataSheet4U.com Philips Semiconductors Product specification 12-bit, 5.0 V, 40 Msps analog-to-digital interface for CCD cameras BLOCK DIAGRAM TDA9965A handbook, full pagewidth VCCD2 SHD 47 46 SHP 45 CLAMP CLAMP TRACK AND HOLD CLPOB 44 CLPADC 43 DGND2 48 AGND4 1 VCCD1 CLKADC DGND1 STDBY D11 42 41 40 39 38 D10 37 IN 2 CLOCK 36 D9 AGND5 STGE AGND1 VCCA1 3 4 5 6 4-BIT DAC 10 35 D8 D7 34 33 D6 TDA9965A AGND2 VCCA2 Vref 7 8 9 12-BIT ADC 12 OUTPUT BUFFER 32 VCCO2 OGND2 31 30 VCCO1 OGND1 PGAOUT 10 PGA REF = 3.2 V 29 28 10-BIT DAC ADCIN 11 26 D5 27 D4 D3 n.c. 12 REGULATOR 16 DEC VRT REF32 INIT-ONPOWER 17 18 VCCA3 AGND3 19 SERIAL INTERFACE 20 SEN SCLK 21 22 23 D0 24 D1 25 D2 13 14 VRB 15 MGU713 SDATA REGEN Fig.1 Block diagram. 2004 Jul 05 3 www.DataSheet4U.com Philips Semiconductors Product specification 12-bit, 5.0 V, 40 Msps analog-to-digital interface for CCD cameras PINNING SYMBOL AGND4 IN AGND5 STGE AGND1 VCCA1 AGND2 VCCA2 Vref PGAOUT ADCIN n.c. REGEN VRB VRT DEC REF32 VCCA3 AGND3 SEN SCLK SDATA D0 D1 D2 D3 D4 D5 OGND1 VCCO1 OGND2 VCCO2 D6 D7 D8 D9 D10 D11 STDBY 2004 Jul 05 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 analog ground 4 data input signal from CCD analog ground 5 clamp storage capacitor pin analog ground 1 analog supply voltage 1 analog ground 2 analog supply voltage 2 ADC clamp reference voltage input; short-circuited to ground via a capacitor PGA amplifier signal output ADC analog signal input; externally connected to pin PGAOUT not connected regulator enable input (active HIGH) regulator reference voltage bottom regulator reference voltage top regulator decoupling; decoupled to ground via a capacitor internal reference voltage; decoupled to ground via a capacitor analog supply voltage 3 analog ground 3 enable input for the serial interface shift register (active LOW) serial clock input for the serial interface DESCRIPTION TDA9965A serial data input: 10-bit PGA gain, 4-bit DAC for the frequency cut-off, 10 low significant bits for the digital ADC clamp and edge pulse control ADC digital output 0 (LSB) ADC digital output 1 ADC digital output 2 ADC digital output 3 ADC digital output 4 ADC digital output 5 digital output ground 1 digital output supply voltage 1 digital output ground 2 digital output supply voltage 2 ADC digital output 6 ADC digital output 7 ADC digital output 8 ADC digital output 9 ADC digital output 10 ADC digital output 11 (MSB) standby control input (active HIGH); all output bits are logic 0 when standby is enabled 4 www.DataSheet4U.com Philips Semiconductors Product specification 12-bit, 5.0 V, 40 Msps analog-to-digital interface for CCD cameras SYMBOL VCCD1 DGND1 CLKADC CLPADC CLPOB SHP SHD VCCD2 DGND2 PIN 40 41 42 43 44 45 46 47 48 digital supply voltage 1 digital ground 1 ADC clock input clamp control pulse input for ADC analog input signal clamp control pulse input at optical black preset sample and hold pulse input data sample and hold pulse input digital supply voltage 2 digital ground 2 DESCRIPTION TDA9965A 42 CLKADC 43 CLPADC 48 DGND2 41 DGND1 44 CLPOB 47 VCCD2 40 VCCD1 38 D11 AGND4 1 IN 2 AGND5 3 37 D10 handbook, full pagewidth 39 STDBY 46 SHD 45 SHP 36 D9 35 D8 34 D7 33 D6 32 VCCO2 31 OGND2 STGE 4 AGND1 5 VCCA1 6 TDA9965AHL AGND2 7 VCCA2 8 Vref 9 30 VCCO1 29 OGND1 28 D5 27 D4 26 D3 25 D2 PGAOUT 10 ADCIN 11 n.c. 12 REGEN 13 VRB 14 VRT 15 DEC 16 REF32 17 VCCA3 18 AGND3 19 SEN 20 SCLK 21 SDATA 22 D0 23 D1 24 MGU715 Fig.2 Pin configuration. 2004 Jul 05 5 www.DataSheet4U.com Philips Semiconductors Product specification 12-bit, 5.0 V, 40 Msps analog-to-digital interface for CCD cameras LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VCCA VCCD VCCO ∆VCC PARAMETER analog supply voltage digital supply voltage digital output supply voltage supply voltage difference between VCCA and VCCD between VCCD and VCCO Vi Io Tstg Tamb Tj Note 1. All supplies are connected together. HANDLING input voltage output current storage temperature ambient temperature junction temperature referenced to AGND −1.0 −1.0 −0.3 −10 −55 −20 − CONDITIONS note 1 note 1 note 1 MIN. −0.3 −0.3 −0.3 TDA9965A MAX. +7.0 +7.0 +7.0 +1.0 +4.0 +7.0 +10 +150 +75 150 V V V V V V UNIT mA °C °C °C Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 76 UNIT K/W 2004 Jul 05 6 www.DataSheet4U.com Philips Semiconductors Product specification 12-bit, 5.0 V, 40 Msps analog-to-digital interface for CCD cameras CHARACTERISTICS VCCA = VCCD = 5 V; VCCO = 3.0 V; fpix = 40 MHz; Tamb = −20 to +75 °C; unless otherwise specified. SYMBOL Supplies VCCA VCCD VCCO ICCA ICCD ICCO analog supply voltage digital supply voltage digital output supply voltage analog supply current digital supply current digital output supply current with internal regulator with internal regulator fpix = 40 MHz; CL = 10 pF on all data outputs; ramp input 4.75 4.75 3.0 − − − 5.0 5.0 3.3 65 19 1 PARAMETER CONDITIONS MIN. TYP. TDA9965A MAX. UNIT 5.25 5.25 5.25 − − − V V V mA mA mA Digital inputs CLOCK INPUT: PIN CLKADC (REFERENCED TO DGND) VIL VIH IIL IIH Zi Ci VIL VIH Ii VIL VIH Ii Vi(IN)(p-p) Ii(IN) tW(SHP) LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current input impedance input capacitance VCLKADC = 0.8 V VCLKADC = 2.0 V 0 2.0 −1 − − − 0 2.0 −2 0 2.0 −10 − −3 Vi(IN) = 1000 mV; 8 transition (98.5%) in 1 pixel; code fco(CTH) = 0000; see Fig.5 − − − − 63 1 − − − − − − 2 − − 0.8 VCCD +1 20 − − 0.8 VCCD +2 V V µA µA kΩ pF CONTROL INPUTS: PINS SEN, SCLK, SDATA, STDBY, CLPOB, CLPADC AND REGEN LOW-level input voltage HIGH-level input voltage input current V V µA V V µA V µA ns SAMPLE AND HOLD INPUTS: PINS SHP AND SHD LOW-level input voltage HIGH-level input voltage input current 0.8 VCCD +10 − +3 − Clamp and Track/Hold (CTH) circuit: pins IN, SHD and SHP CTH input voltage (peak-to-peak value) input current SHP pulse width 2004 Jul 05 7 www.DataSheet4U.com Philips Semiconductors Product specification 12-bit, 5.0 V, 40 Msps analog-to-digital interface for CCD cameras SYMBOL tW(SHD) PARAMETER SHD pulse width CONDITIONS Vi(IN) = 1000 mV; 8 transition (98.5%) in 1 pixel; code fco(CTH) = 0000; see Fig.5 code fco(CTH) 0000 0001 0010 0100 1000 1111 th(IN-SHP) CTH input hold time compared to control pulse SHP CTH input hold time compared to control pulse SHD see Fig.5 − − − − − − − 7 12 16 22 32 49 3 MIN. − TYP. TDA9965A MAX. − UNIT ns − − − − − − − ns ns ns ns ns ns ns th(IN-SHD) see Fig.5 − 3 − ns Programmable Gain Amplifier (PGA) output: pin PGAOUT VPGAOUT(p-p) PGA output amplifier dynamic voltage level (peak-to-peak value) PGA output amplifier black code C(CLP) = 0 level voltage PGA output amplifier output impedance PGA output current drive minimum gain of PGA circuit maximum gain of PGA circuit fpix at 10 kHz for minimum and maximum values static code GPGA = 0 code GPGA ≥767 − 2000 − mV