TV HORIZONTAL PROCESSOR

TDA1180P TV HORIZONTAL PROCESSOR s s s s s s s s s NOISE GATED HORIZONTAL SYNC SEPARATOR NOISE GATED VERTICAL SYNC SEPARATOR HORIZONTAL OSCILLATOR WITH FREQUENCY RANGE LIMITER PHASE COMPARATOR BETWEEN SYNC PULSES AND OSCILLATOR PULSES (PLL) PHASE COMPARATOR BETWEEN FLYBACK PULSES AND OSCILLATOR PULSES (PLL) LOOP GAIN AND TIME CONSTANT SWITCHING ( VCR) COMPOSITE BLANKING AND KEY PULSE GENERATOR PROTECTION CIRCUITS OUTPUT STAGES WITH HIGH CURRENT CAPABILITY DIP16 (Plastic Package) ORDER CODE : TDA1180P DESCRIPTION The TDA1180P is a horizontal processor circuit for b.w. and colour monitors. It is a monolithic integrated circuit encapsulated in 16-lead dual in-line plastic package. PIN CONNECTIONS SUPPLY VOLTAGE NEGATIVE OUTPUT POSITIVE OUTPUT PROTECTION CIRCUIT INPUT PHASE SHIFTER FILTER FLYBACK INPUT KEY AND BLANKING PULSE OUTPUT SYNC. SEPARATOR INPUT 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 GROUND OSCILLATOR CONTROL CURRENT OSCILLATOR CONTROL CURRENT OUTPUT TIME CONSTANT SWITCH COINCIDENCE DETECTOR VERTICAL SYNC. OUTPUT VERTICAL SYNC. SEPARATOR INPUT 1180P-01.EPS May 1993 1/12 2/12 VS VS TDA1180P BLOCK DIAGRAM VS AAAA AAAA 10 7 6 1 5 4 9 Vertical Sync. Separator Pulse Shaper Vertical Sync. Output Stage Composite Key and Blanking Pulse Generator AAAA AAAA Phase Comparator (Oscillator Flyback) Phase Shifter and Pulse Shaper Protection Switch 2 VS Pulse Shaper Noise Video Signal Gate 8 Sync. Separator Oscillator Sync. Gate Vertical Sync. Blanking Phase Comparator (Oscillator Sync.) Under Voltage Protection AAAA AAAA Coincidence Detector Time Constant and Control Current Switch Voltage Limiter Output Stage 3 11 VCR 12 13 15 14 16 VS Frequency AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA 1180P-02.EPS TDA1180P ABSOLUTE MAXIMUM RATINGS Symbol VS V2 V4 V8 V9 V11 I2 I3 I6 I7 I10 Ptot Tstg , Tj Supply voltage (Pin 1) Voltage at Pin 2 Voltage at Pin 4 Voltage at Pin 8 Voltage at Pin 9 Voltage at Pin 11 Pin 2 peak current Pin 3 peak current Pin 6 current Pin 7 current Pin 10 current Total power dissipation at Tamb ≤ 70 C Storage and junction temperature o Parameter Value 15 18 VS - 6 , VS ±6 VS 1 0.5 30 20 30 1 - 40 , + 150 Unit V V V V A A mA mA W o 1180P-01.TBL 1180P-03.TBL 1180P-02.TBL mA C THERMAL DATA Symbol Rth (j-a) Parameter Thermal Resistance Junction-Ambient Max Value 80 Unit o C/W ELECTRICAL CHARACTERISTICS (refer to the test circuit, VS = 12V, TA = 25oC, unless otherwise specified) Symbol VS IS VS Supply current Supply voltage at which the output pulses (at pin 2 and 3) are switched off Parameter Supply voltage range I3 = 0 Test conditions Min. 9.5 Typ. 12 42 Max. 13.2 52 4 Unit V mA V HORIZONTAL SYNC. SEPARATOR VI V8 I8 I8 Peak to peak input signal Input switching voltage Input switching current Leakage current I8 = 80 µA V8 = 1.4V V8 = -5V 1 3 1.5 10 1 6 V V µA µA VERTICAL SYNC. SEPARATOR VI V9 I9 I9 V10 R10 tLV tLV tV Peak to Peak Input Signal Input Switching Voltage Input Switching Current Leakage Current Vertical Sync. Pulse Output Voltage Output Resistance Delay between Leading Edge of Input and Output Signals Delay between Trailing Edge of Input and Output Signals Vertical Sync Pulse Duration I9= 80µA V9 = 1.4V V9 = -5V No Load Pin10 11 10 17 50 190 1 3 1.5 5 1 6 V V µA µA V kΩ µs µs µs 3/12 TDA1180P ELECTRICAL CHARACTERISTICS (continued) (refer to the test circuit, VS = 12V, TA = 25oC, unless otherwise specified) Symbol PROTECTION CIRCUIT V4 R4 I4 Input Voltage for Switching off the Output Pulses Input Resistance Input Current 5 Output Pulses OFF Output Pulses ON 0.5 1 200 kΩ µA V Parameter Test conditions Min. Typ. Max. Unit FLYBACK PULSE V6 V6 I6 Input Threshold Voltage of Blanking Generator Input Threshold Voltage of Phase Comparator Input Switching Current V6 ≥ 1.7V 1.8 7.6 0.45 V V mA OUTPUT PULSE V3 I3 R3 Peak-to-Peak Output Voltage Output Current Output Resistance I3 = 150 mApp V3 = 5V At Leading Edge of output pulse At Training Edge of Output Pulse 20 10 500 3 20 22 26 V mA Ω Ω µs tp Output Pulse Duration COMPOSITE BLANKING AND KEY PULSE V7k V7B R7 tsk tk tfb Key Pulse Output Peak Voltage Blanking Pulse Output Voltage Output Resistance Phase Relation Between Trailing Edge of Key Pulse and Middle of Sync. Input Pulse Key Pulse Duration Delay between Flyback Pulse and Blanking Pulse V6 = 1.7V 3.5 9 4.2 11 4.5 100 2.7 3.8 0.2 4.8 V V Ω µs µs µs µs µs INTERNAL GATING PULSE tg t Gating Pulse Duration Phase Relation between Middle of Sync. Pulse and Trailing and Leading Edge of Gating Pulse 7.5 3.75 COINCIDENCE DETECTOR V11 I11 Output Voltage Peak Output Current With Coincidence Without Coincidence 6.8 4 0.5 V V mA VCR SWITCH V11 - I11 I11 Input Voltage Output Current Output Current 0 to 4 or 8.5 to 12 35 0.4 V µA mA TIME CONSTANT SWITCH V12 R12 Output Voltage Output Resistance 4.5V < V11 < 8V V11 > 8.5V or V11 < 4V 3 100 40 V Ω kΩ 1180P-04.TBL 4/12 TDA1180P ELECTRICAL CHARACTERISTICS (continued) (refer to the test circuit, VS = 12V, TA = 25oC, unless otherwise specified) Symbol OSCILLATOR V14 V14 I14 I14 V15 I15 fO ∆fO fO ∆fO ∆I15 ∆fO Low Level Threshold Voltage High Level Threshold Voltage Charge Current Discharge Current Current Source Supply Voltage Current Source Supply Current Free Running Frequency Adjustment Range Frequency Control Sensitivity Frequency Change when VS Drops to 4V 5.4 8.2 0.6 0.3 3 0.3 15625 ± 10 52 ± 10 V V mA mA V mA Hz % Hz µA % Parameter Test conditions Min. Typ. Max. Unit OSCILLATOR-FLYBACK PULSE PHASE COMPARATOR V5 I5 I5 tD ∆t ∆tD Control Voltage Range Peak Control Current Input Current (blocked Phase Detector) Permissible Delay between Output Pulse Leading Edge and Flyback Pulse Leading Edge Static Control Error tp - tf 0.2 -0.6 9.4 to 8.2 +0.6 5 V mA µA µs % SYNC PULSE-OSCILLATOR PHASE COMPARATOR V13 Control Voltage Range 4.6 to 1.4 +2 -2.2 2 ± 700 -2 V I13 ∆f ∆t f Control Peak Current Phase Lock Loop Gain Catching and Holding Range mA kHz µs Hz OVERALL PHASE RELATIONSHIP tO ∆V5 ∆tO ∆I5 ∆tO Phase Relation between Middle of Flyback Pulse and Middle of Sync. Pulse Adjustment Sensitivity Adjustment Sensitivity 2.2 65 16 µs mV µs µA µs 5/12 1180P-05.TBL TDA1180P TEST CIRCUIT Sandcastle Output Vert. Sync. Output +V S R8 47kΩ R3 2.2MΩ C1 470nF 9 R1 2.2kΩ 2 10 7 6 5 C8 220nF 4 1 Flyback Input (100V) +V S TDA1180P Video Signal Input R2 2.7kΩ 8 C3 220nF C2 100pF +V S C4 100nF R4 1.5MΩ 11 12 R7 R6 3.6kΩ R5 820kΩ C5 680nF 1.2kΩ C6 4.7µF C7 10nF 13 R9 100kΩ R10 10kΩ R11 82kΩ C9 4.3nF 15 14 16 3 Output Pulse R12 +V S 22kΩ P2 22kΩ Frequency Figure 1 : Vertical Sync. Output Pulse tV 6/12 1180P-04.EPS t LV t TV 1180P-03.EPS TDA1180P Figure 2 : Relation Ship of Main Waveform Phases Flyback Input Pulse to tf Video Input Signal Phase Comparator Driving Pulse Separated Sync. Pulse tg Gate Pulse t t td Sandcastle Output Pulse V7K t SK tK V7B tp Output Pulse Pin 3 1180P-05.EPS 7/12 TDA1180P Figure 3 : Free Running Frequency versus Supply Voltage f O (kHz) 16 Figure 4 : Loop Gain f O (kHz) 1 15.625 15.5 0 1180P-06.EPS 15 0 2 4 6 8 10 12 VS (V) 14 16 ϕ (µs) -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 APPLICATION INFORMATION Pin 1 - Positive supply The operating supply voltage of the device ranges from 10V to 13.2V Pin 2 and 3 - Output The outputs of TDA1180P are suitable for driving transistor output stages, they deliver positive pulse at Pin 3 and negative pulse at Pin 2. The negative pulse is used for direct driving of the output stage, while positive pulse is useful when a driver stage is required. The rise and fall times of the output pulses are about 150 ns so that interference due to radiation are avoided. Furthermore the output stages are internally protected against short circuit. Pin 4 - Protection circuit input By connecting Pin 4 of the IC to earth the output pulses at Pin 2 and 3 are shut off ; this function has been introduced to produced to protect the final stages from overloads. The same pulses are also shut off when the supply voltage falls below 4V. Pin 5 - Phase shifter filter To compensate for the delay introduced by the line final stages, the flyback pulses to Pin 6 and the oscillator waveform are compared in the oscillatorflyback pulse phase comparator. The result of the comparison is a control current which, after it has been filtered by the external capacitor connected to Pin 5, is sent to a phase shifter which adequately regulates the phase of the output pulses. 8/12 The maximum phase shift allowed is: td = tp - tf where tf is the flyback pulse duration. Pin 5 has high input and output resistance (current generator). Pin 6 - Flyback input The flyback pulse drives the high impedance input through a resistor in order to limit the input current to suitable maximum values. The flyback input pulses are processed by a double threshold circuit; this generates the blanking pulses by sensing low level flyback voltage and the pulses to drive the phase comparator by sensing high level flyback voltage, therefore phase jitter caused by ringing normally associated with the flyback pulse, is avoided. Pin 7 - Key and blanking pulse output The key pulse for taking out the burst from the chrominance signal is generated from the oscillator ramp and has therefore a fixed phase position with respect to the sync. The key pulse is then added internally to the blanking pulse obtained by correctly forming the flyback pulse present at Pin 6. The sum of the two signals (sandcastle pulse) is available on low impedance at output Pin 7. Pin 8 and 9 - Sync separators inputs The video signal is applied by means of two distinct biasing networks to pins 8 and 9 of the IC and therefore to the respective vertical and horizontal sync separators. The latter take the sync pulses out of the video signal and make them available to the rest of the circuit for further proces