3-Line Digital Comb Filter

www.DataSheet4U.com TC90A80N/F TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC90A80N,TC90A80F 3-Line Digital Comb Filter for VCR, YNR/CNR, and Skew Correctors (NTSC) The TC90A80N/F is a 3-line digital Y/C (luminance/ chrominance) separation IC for VCR. In addition to YNR and CNR used for noise reduction in the playback signal, the IC incorporates skew correctors for special playback. The IC is then suitable for processing S-VHS recorded playback signals. TC90A80N Features • • • • • • • • • • • • • • • • • • TV format: NTSC (3.58) Dynamic comb filter YNR circuit CNR circuit Luminance signal non-linear vertical edge corrector (with coring function) Luminance signal horizontal frequency characteristic corrector (with coring function) Luminance signal line noise canceller Record/playback input switch circuit (switches between Y/C and Y inputs) Y and C input pins, independently one another (Y: sync tip clamp; C: center bias) Re-mixer circuit after Y/C sharpness processing Skew detector and correctors (NTSC ×5 Mode: in units of 0.2 H) 8-bit 4 fsc AD converter (2 channels) 10-bit 8 fsc DA converter (2 channels) 1-H delay line (2 channels) I2C bus control I2C bus decode output pin (High/Low) 5-V single power operation Weight SDIP28-P-400-1.78 : 1.7 g (typ.) SOP28-P-450-1.27 : 0.8 g (typ.) TC90A80F PLL detector for switching frequencies (fsc, 2 fsc, 4 fsc and 8 fsc clock inputs) 1 2002-12-04 www.DataSheet4U.com TC90A80N/F Block Diagram HD + PV OUT C-OUT Y-OUT Mode1 fsc-IN +5 V (PLL) SDA 0.1 µF 0.1 µF 0.01 µF 0.01 µF 330 Ω 100 µF 680 pF 0.1 µF 24 23 VDD2 PLL detector 22 VCO 21 VSS5 1/2 8 fsc 20 VDD5 4 fsc Skew Delay N.L V-enhancer YNR Memory YCS Memory [B] [A] Dynamic comb Filter YNR 0.01 µF 28 27 DAC 26 VSS2 25 DAC 19 18 17 16 I2C bus (8 fsc) Interpolation Delay Adj (±210 @70 ns) CNR YCS CNR Mix ON + Mix OFF 1/8 1/4 1/2 0 Ped. CLIP LPF + Killer Y-EQ Y-N.C C-N.C Skew corrector BPF Bias Sync Clamp TEST 7 8 9 ADC ADC Skew corrector Memory [B] Skew detector VSS1 5 VSS3 10 VDD3 12 VDD4 13 SCL 15 PG 14 0.01 µF 0.01 µF 0.01 µF 0.01 µF 1 2 VDD1 3 4 6 11 0.01 µF 0.47 µF 0.47 µF 0.01 µF 47 µF KILLER /PV IN C.SYNC IN +5 V (digital) 0.1 µF 100 µF +5 V (ADC) C-IN Y/C-IN Y-IN 2 2002-12-04 www.DataSheet4U.com TC90A80N/F Pin Functions Pin No. Pin Name Function DC Level (V) Interface Circuit ADC bias pin 1 BIAS Connect a 0.01-µF capacitor between this pin and pin 5 (VSS1). 1.3 1 Sets upper limit of range D for ADC. 2 VRT Connect a 0.01-µF capacitor between this pin and pin 5 (VSS1). The output voltage is held at internal level. 3.16 2 20 Ω 3 VDD1 ADC power supply pin (analog) Apply the same voltage as that of pin 23 (VDD2). 5.0 Internally connected to pin 23 (VDD2). 4 CIN 5 VSS1 ADC GND pin (analog) Set the same voltage as that of pin 26 (VSS2). 0.0 Internally connected to pin 26 (VDD2). Sets lower limit of range D for ADC. 6 VRB Connect a 0.01-µF capacitor between this pin and pin 5 (VSS1). The output voltage is held at internal level. 1.83 6 20 Ω Luminance signal input pin (I2C Bus function: NR) 7 YIN Because sync tip clamp is internally used, the signal should be applied after cutting the DC component using a capacitor of around 0.47 µF. Sync Tip NR Mode : 1.86 YCS Mode : 1.83 7 20 Ω 20 Ω Pin for reset control and test control when shipping. 8 TEST Reset control: Applying pulse of 10 µs or longer while the pin is at High with power on resets all the I2C bus settings to 0. For normal use, set the pin to Low. 0.0 8 150 Ω 3 660 Ω 1.14 kΩ ADC bias pin 2002-12-04 15 kΩ Because the signal is internally center-biased, it should be applied after cutting the DC component using a capacitor of around 0.01 µF. 2.5 4 20 Ω 15 kΩ 15 kΩ Chrominance signal input pin (I2C Bus function: NR) 1.14 kΩ 660 Ω ADC bias pin www.DataSheet4U.com TC90A80N/F Function DC Level (V) Interface Circuit Pin No. Pin Name Composite video signal input pin (I2C Bus function: YCS) 9 YCIN Because sync tip clamp is internally used, the signal should be applied after cutting the DC component using a capacitor of around 0.47 µF. Sync Tip YCS Mode : 1.86 NR Mode : 1.83 9 20 Ω 20 Ω 10 VSS3 Logic and DRAM GND pin (digital) Separate digital VSS from analog VSS. Killer control and pseudo vertical pulse (PV) input pin (M or H polarity can be selected using I2C Bus.) 0.0 ― 11 KIPVIN In Killer mode, Y/C separation, vertical enhancer, CNR, and YNR are halted. PV input: Vertical mask signal for detecting skew. Apply PV which is synchronous with input video signal. For normal use, or not in use, set the pin to Low. Logic power supply pin (digital) Separate digital VDD from analog VDD. DRAM power supply (digital) Separate digital VDD from analog VDD. 3-level input 11 700 Ω 3.2 V 1.4 V 12 VDD3 5.0 ― 13 VDD4 5.0 ― Composite sync pulse input pin for detecting skew 14 CSYNCIN Apply sync separation pulse (positive polarity pulse) of the input video signal. When not in use, set to Low. ― 14 700 Ω 15 SCL I C bus clock input pin 2 ― 15 700 Ω 16 SDA I C bus data input/output pin 2 ― 16 700 Ω ACK Sync output pin In Skew Correction Mode: Output can be selected as either HD pulse which is synchronous with output video signal or signal mixed with input PV. In modes other than Skew Correction, drives out C Composite sync pulse. Use for later-stage circuit such as 3DNR. 17 HDPVOUT ― 17 4 2002-12-04 www.DataSheet4U.com TC90A80N/F Function DC Level (V) Interface Circuit Pin No. Pin Name MODE1 output pin 18 MODE1 High or Low output voltage signal can be selected using I2C bus. Use for controlling peripheral circuits. ― 18 Clock input pin 19 FSC Apply sine wave locked to the frequency of the input video burst signal. One of the four frequencies (fsc, 2fsc, 4fsc, and 8fsc) can be selected using I2C bus. 2.45 19 170 Ω 300 kΩ 20 21 VDD5 VSS5 PLL power supply pin (analog) PLL GND pin (analog) 5.0 0.0 ― ― VCO control pin 22 FIL Connect lag-lead filter between this pin and pin 21 (VSS5). 3.0 22 90 Ω 100 Ω 23 VDD2 DAC power supply pin (analog) Apply the same voltage as that of pin 3 (VDD1). 5.0 Internally connected to pin 3 (VDD1). DAC bias 2 pin 24 VB2 Connect a 0.01-µF capacitor between this pin and pin 26 (VSS2). 3.4 24 Luminance signal output pin 25 YOUT When Y/C Re-Mix Mode is selected using I2C bus, this pin drives out a composite video signal. Sync Tip : 2.46 25 26 VSS2 DAC GND pin (analog) Set the same voltage as that of pin 5 (VSS1). 0.0 Internally connected to pin 5 (VSS1). 5 2002-12-04 400 Ω www.DataSheet4U.com TC90A80N/F Function DC Level (V) Interface Circuit Pin No. Pin Name Chrominance signal output pin 27 COUT When Y/C Re-Mix Mode is selected using I2C bus, this pin drives out no signal. 3.7 27 DAC bias pin 1 28 VB1 Connect a 0.01-µF capacitor between this pin and pin 26 (VSS2). 1.6 28 Note 1: Caution regarding external circuits (component allocation) for improving S/N and stabilizing operation: Power supply pins are paired with GND pins. Read the section on Pin Functions and connect a ceramic capacitor and an electrolytic capacitor directly between power supply and GND pins. Toshiba recommend using a capacitor of 0.1 µF or more between analog power supply and GND pins. (For digital pins, use a 0.01-µF capacitor.) 6 2002-12-04 400 Ω www.DataSheet4U.com TC90A80N/F IC Control Specifications • • • • Functions and characteristics of this IC are set using the I2C bus. The data transfer format conforms to the Philips I2C bus format. When reset signal is applied, the following DATA bits are all cleared to 0. Data transfer format S Slave address (8 bits) A DATA1 A DATA2 A DATA3 A DATA4 A P Slave address: B4H S: Start condition, A: Acknowledgement, P: Stop condition • Outline of I2C bus format I2C bus transfers data between ICs using two lines: data (SDA) and clock (SCL). The I2C bus starts according to the start condition and ends according to the stop condition. The start condition is satisfied if SDA changes from High to Low when SCL is High. The stop condition is satisfied if SDA changes from Low to High when SCL is High. The length of data to be transferred is 8 bits. Data are transferred via the SDA line. An acknowledge (ACK) bit is required after a data byte. The bus line must be pulled up to the power supply level using a resistor. When SCL is High, data must not be changed. • I2C bus control signal timing Don’t change the data while clock is in High level. tf Date tr tBUF Clock tf tSU; DAT tHD; DAT tHIGH tLOW tr Start Condition tHD; STA tSU; STO Stop Condition Characteristics SCL clock frequency Hold time to satisfy start condition SCL clock Low period SCL clock High period Data hold time Data setup time SDA/SCL signal rise time SDA/SCL signal fall time Stop condition setup time Bus free time between stop and start conditions Symbol fSCL tHD; STA tLOW tHIGH tHD; DAT tSU; DAT tr tf tSU; STO tBUF Min 0 4.0 4.7 4.0 0 250 ― ― 4.0 4.7 Max 100 ― ― ― 3.45 ― 1000 300 ― ― Unit kHz µs µs µs µs ns ns ns µs µs Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. 7 2002-12-04 www.DataSheet4U.com TC90A80N/F I2C Bus Control Data List I2C Bus Control List D7 Function DATA1 0: YCS 1: NR D6 Skew 0: OFF 1: ON CNR Gain DATA2 00: OFF 01: 0.5 10: 0.625 11: 0.75 Y-EQ Gain DATA3 00: OFF 01: 0.125 10: 0.25 11: 0.5 000: 1 001: 3 010: 5 000: ±0 ns 001: −70 010: −140 D5 D4 C-Delay 011: −210 100: ±0 ns 101: +70 CNR Lim. 011: 7 100: 9 101: 11 Y-EQ/N.C Lim 00: OFF 01: H2 (L4) 10: H4 (L8) 11: H8 (L14) 110: 13 111: 15 YNR Corr. 0: ON 1: OFF 110: +140 111: +210 D3 Slave add