315-W Mono BTL Digital Amplifier Power Stage

www.DataSheet4U.com TM TAS5261 www.ti.com SLES188 – AUGUST 2006 315-W Mono BTL Digital Amplifier Power Stage FEATURES • Total Output Power – 125 W Into 8 Ω at <0.09% THD+N – 220 W Into 6 Ω at 10% THD+N – 315 W Into 4 Ω at 10% THD+N 110-dB SNR (A-Weighted with TAS5518 modulator) Supports Pulse-Width Modulation (PWM) Frame Rates of 192 kHz to 384 kHz Resistor-Programmable Current Limit Integrated Self-Protection Circuit Including: – Under Voltage Protection – Over Temperature Warning and Error – Over Load Protection – Short Circuit (OC) Protection – PWM Activity Dectector Power-On Reset (POR) to Eliminate System Power-Supply Sequencing Thermally-Enhanced Package DKD (36-pin PSOP3) EMI Compliant When Used With Recommended System Design Error Reporting 3.3-V and 5-V Compliant The TAS5261 has complete protection circuitry integrated on chip, safeguarding the device and speakers against fault conditions that could damage the system. These protection features are short-circuit protection, overcurrent protection, undervoltage protection, and a loss of pulse-width modulation (PWM) input signal (PWM Activity Detector). A power-on reset (POR) circuit is used to eliminate power-supply sequencing that is normally required for most H-bridge designs. OUTPUT POWER vs PVDD_x SUPPLY VOLTAGE 330 300 270 PO − Output Power − W 240 210 180 150 120 90 60 30 0 0 5 10 15 20 25 30 35 40 45 50 G001 • • • • TC = 75°C THD+N at 10% • • • • • • • • 6Ω 4Ω APPLICATIONS AV Receivers DVD Receivers Mini/Micro Component Systems Home Theater Systems 8Ω PVDD Supply Voltage − V DESCRIPTION The TAS5261 is a high-performance, integrated mono digital amplifier power stage designed to drive 4-Ω to 8-Ω speakers with low harmonic distortion. This system requires only a simple, passive demodulation filter to deliver high-quality, high-efficiency audio amplification. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated TAS5261 www.ti.com SLES188 – AUGUST 2006 DEVICE INFORMATION The TAS5261 is available in a thermally-enhanced 36-pin PSOP3 PowerPAD™ package. The heat slug is located on the top side of the device for convenient thermal coupling to a heat sink. DKD PACKAGE (TOP VIEW) BST_A GVDD_A OTW SD RESET PWM_A OC_ADJ GND AGND VREG M3 M2 M1 PWM_B VDD GND GVDD_B BST_B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 PVDD_A PVDD_A PVDD_A PGND PGND PGND OUT_A OUT_A OUT_A OUT_B OUT_B OUT_B PGND PGND PGND PVDD_B PVDD_B PVDD_B P0018-02 2 Submit Documentation Feedback TAS5261 www.ti.com SLES188 – AUGUST 2006 DISSIPATION RATINGS PARAMETER RθJC RθJC Pad area CONDITION BTL channel (four transistors) One transistor TYPICAL (DKD) 0.6°C/W 2.38°C/W 80 mm2 Protection Mode Protection modes are selected by shorting M1, M2, and M3 to VREG or GND. Table 1. Protection Modes MODE PINS M3 (1) 0 0 0 0 M2 0 0 1 1 M1 0 1 0 1 PROTECTION MODE Full protection (default) Reserved OC latching mode Reserved (1) M3 is reserved and always should be connected to board GND. Submit Documentation Feedback 3 TAS5261 www.ti.com SLES188 – AUGUST 2006 TERMINAL FUNCTIONS TERMINAL NAME AGND BST_A BST_B GND GVDD_A GVDD_B M1 M2 M3 OC_ADJ OTW OUT_A OUT_B PGND PWM_A PWM_B PVDD_A PVDD_B RESET SD VDD VREG PIN NO. 9 1 18 8, 16 2 17 13 12 11 7 3 28, 29, 30 25, 26, 27 22, 23, 24, 31, 32, 33 6 14 34, 35, 36 19, 20, 21 5 4 15 10 I/O I P I I P I I I I I O O O P I I P P I O I O Analog ground Bootstrap, A side Bootstrap, B side Power ground Gate-drive voltage supply, A side Gate-drive voltage supply, B side Mode-selection 1 (LSB) Mode-selection 2 (MSB) Reserved Overcurrent threshold programming Overtemperature warning. Open drain, active low. Output, half-bridge A Output, half-bridge B Power ground PWM for half-bridge A PWM Input for half-bridge B PVDD supply for half-bridge A PVDD supply for half-bridge B Reset. Active low. Shutdown. Open drain, active low. Input power supply Internal voltage regulator DESCRIPTION 4 Submit Documentation Feedback TAS5261 www.ti.com SLES188 – AUGUST 2006 GVDD (12 V) and VDD (12 V) GND PVDD (0–50 V) PVDD Power-Supply Decoupling GVDD, VDD, and VREG Power-Supply Decoupling 2 Hardwire Overcurrent Limit 6 6 GND_A, B GND GVDD_A, B PVDD_A, B VDD VREG GND H-Bridge OC_ADJ Output OUT_A OUT_B R1 Right Output PWM_A Mono BTL H-Bridge TAS55XX Overtemp_warning R2 2nd-Order L-C Output Filter for Each H-Bridge 4–8 W (3 W Min) PWM_B Left Output M1 BST_A BST_B Bootstrap Capacitors M3 RESET SD OTW System Microcontroller RESET_H-Bridge SD OTW RESET RESET M2 Shutdown Shutdown Hardwire Mode Control L1 PWM_A Overtemp_warning PWM_B Mono BTL H-Bridge H-Bridge Output L2 OUT_A OUT_B 2nd-Order L-C Output Filter for Each H-Bridge 4–8 W (3 W Min) GVDD_A, B PVDD_A, B M1 Hardwire Mode Control M2 M3 BST_A GND_A, B OC_ADJ 6 6 2 50 V System Power Supplies GND 12 V PVDD (0–50 V) PVDD Power-Supply Decoupling GVDD, VDD, and VREG Power-Supply Decoupling VDD VREG GND BST_B Bootstrap Capacitors GND Hardwire Overcurrent Limit GND GVDD (12 V) and VDD (12 V) AC B0101-01 Figure 1. Typical System Block Diagram Submit Documentation Feedback 5 TAS5261 www.ti.com SLES188 – AUGUST 2006 OTW PROTECTION & I/O LOGIC VDD POWER-UP RESET UVP SD VREG VREG M1 AGND TEMP SENSE GVDD_A GVDD_B GND M2 M3 OVER-LOAD PROT . CB3C CURRENT SENSE OC_ADJ RESET GVDD _B PWM ACTIVITY DETECTOR BST_B PVDD_B (x3) PWM RECEIVER TIMING CONTROL OUT_B (x3) PGND (x3) PWM_B CONTROL GATE-DRIVE GVDD _A BST_A PVDD_A (x3) PWM RECEIVER TIMING CONTROL PWM_A CONTROL GATE-DRIVE OUT_A (x3) PGND (x3) Figure 2. Functional Block Diagram 6 Submit Documentation Feedback TAS5261 www.ti.com SLES188 – AUGUST 2006 ORDERING INFORMATION TA 0°C to 70°C PACKAGE TAS5261DKD DESCRIPTION 36-pin PSOP3 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN VDD to AGND GVDD_x to AGND PVDD_x to PGND_x (2) OUT_x to PGND_x (2) BST_x to PGND_x (2) BST_x to GVDD_x (2) VREG to AGND PGND_x to GND PGND_x to AGND GND to AGND PWM_x, OC_ADJ, M1, M2, M3 to AGND RESET, SD, OTW to AGND Maximum continuous sink current (SD, OTW) Maximum operating junction temperature range, TJ Storage temperature range, Tstg Lead temperature 1,6 mm (1/16 in) from case for 10 s Minimum pulse duration, low – minimum pulse width must be ensured by the PWM processor (1) (2) 50 0 –65 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 MAX 13.2 13.2 71 71 79.7 66.5 4.2 0.3 0.3 0.3 4.2 7 9 150 150 260 UNIT V V V V V V V V V V V V mA °C °C °C ns Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are only stress ratings, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. These voltages represent the dc voltage + peak ac waveform measured at the terminal of the device in all conditions. Submit Documentation Feedback 7 TAS5261 www.ti.com SLES188 – AUGUST 2006 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN PVDD_x GVDD_x VDD RL RL LDEM fS t(low) CBS RBS RCBS DCLMP DTVS CPVDD RAGND R TJ (1) Half-bridge supply voltage Gate-drive power supply Digital regulator supply voltage Resistive load impedance, bridge-tied load (BTL) Resistive load impedance, BTL, ROC = 22kΩ, PVDD = 50V, (no current limiting) Minimum output filter inductance under both operating and short-circuit conditions, with appropriate OC_ADJ resistor value PWM frame rate Minimum low-state pulse duration per PWM frame, noise shaper enabled Bootstrap capacitor, selected value supports fs = 192 kHz to 384 kHz Bootstrap series resistor - 1/4 W Bootstrap snubber - 1/4 W Ultra-Fast Recovery Clamping Diode, Average forward current = 1A, Maximum repetitive reverse voltage = 200V (ES1D, mfg:Fairchild) Transient Voltage Suppressor, 600W @ 1mS (P6SMB62AT3, mfg: ON Semiconductor) PVDD Close Decoupling Capacitor, two capacitors AGND resistor - 1/4 W Optional external pullup resistor to +3.3V or +5 V for SD and OTW Junction temperature 3.3 0 3 5 192 50 33 1.5 4.7 470 15 62 100 3.3 4.7 125 10 384 0 10.8 (1) 10.8 (1) NOM 50 12 12 4-16 MAX 52.5 13.2 13.2 UNIT V V V Ω Ω µH kHz ns nF Ω Ω pF nS V nF Ω kΩ °C GVDD operation below 10.8 V significantly reduces efficiency of the output MOSFET stage and requires a larger heatsink. For the purpose of noise margin, the UVP level is set lower to provide an increased noise margin, however, TI recommends a nominal dc voltage of 12 V for GVDD. AUDIO CHARACTERISTICS Audio frequency = 1 kHz, PVDD_x = 50 V, GVDD_x = 12 V, VDD = 12 V, RL = 8 Ω , fs = 384 kHz, OC_ADJ = 22 kΩ, TC= 75°C, output filter is LDEM = 10 µH, CL = 1 µF (unless otherwise noted). Audio performance is recorded as a chipset, TAS5518 as front end with an effective modulation index of 96.1% and TAS5261 as the power stage. PCB and system configuration are in accordance with recommended design guidelines. PARAMETER PO Unclipped power output TEST CONDITIONS RL = 8 Ω, f = 1 kHz RL = 6 Ω, f = 1 kHz RL = 4 Ω, f = 1 kHz RL = 8 Ω, f = 1 kHz, THD = 10% PO Maximum power output RL = 6 Ω, f = 1 kHz, THD = 10% RL = 4