DIGITAL AUDIO PROCESSOR

www.DataSheet4U.com TAS3208 DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE www.ti.com SLES201A – JANUARY 2007 – REVISED FEBRUARY 2007 FEATURES • Audio Input/Output – Three Synchronous Serial Audio Inputs (Six Channels) – Two Synchronous Serial Audio Outputs (Four Channels) – Input and Output Data Formats: 16-, 20-, or 24-Bit Data Left, Right, and I2S – SPDIF Transmitter – 64 × Fs Bit Clock Rate – 512 × Fs XTAL Input for Master-Mode Clock Rates – 256 × Fs MCLKIN for Slave-Mode Clock Rates – Ten Multiplexed Stereo Analog Inputs Selectable Into One Stereo ADC and Three Stereo Line Outputs – High-Quality 93 dB DNR (Typical) ADC Channel Performance (Two Channels) – A Single Ended Analog Stereo Line Driver Output With 1 of 11 Selectable Inputs, 10-kΩ, 100-pF Drive Capability (Typical Output Level: 1-V RMS) – Three Stereo Audio DACs – High-Quality 96-dB DNR (Typical) DAC Channel Performance (Six Channels) – Stereo Headphone Amplifier – 24 mW Power Output Into 16 Ω, 100 pF Audio Digital Signal Processor – Programmable Functionality – – – – • • • 135-MHz Operation 48-Bit Data Path With 76-Bit Accumulator Hardware Single Cycle Multiplier (28 × 48) Two Memory Loads and One Memory Store Per Cycle – Usable 768 Data RAM Words (48 Bit), Usable 1K Coefficient RAM (28 Bit) – Usable 2.5K Program RAM – 360 mS @ 48KHz, 17280 Words 24-Bit Delay Memory for Video Sync System Control Processor – Embedded 8051 WARP Microprocessor – Programmable Using Standard 8051 C Compilers – 16K Words of Program RAM (8 Bit) – Programmable Using Standard 8051 C Compilers – 2048 Words of Data RAM (8 Bit) – 256 Words of Internal RAM (8 Bit) – Programmable Functionality General Features – Easy to Use Control Interface – I2C Serial Control Master and Slave Interface – Control Interface Operational Without External MCLK Input – Single 3.3-V Power Supply – Integrated Regulators – 100-Pin TQFP Package Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated TAS3208 DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE SLES201A – JANUARY 2007 – REVISED FEBRUARY 2007 www.ti.com TQFP PACKAGE (TOP VIEW) DVSS 1 / REG_ V EN STEST Test Test GPIO4 GPIO3 MCLKOUT LRCLKOUT SCLKOUT SDOUT 1 SDOUT 2/ SPDIFOUT 1 2 3 4 4 5 5 6 7 8 9 10 11 12 13 14 15 16 17 17 18 18 19 19 20 20 21 22 23 24 25 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 2 6 2 7 2 8 2 9 3 0 3 1 3 2 0 VD 1 0D D 1 9 AD _ S 9 V DO C 9 V_N 8 RA A 9 X A_ U 7 T LO T 9 X A_N 6 T LI 9 A S _ SD 5 V SE 9 AD _P 4 V DH 9 HO T 3 P UR 9 A S_ P 2 V SH 9 HO T 1 P UL 9 AD _P 0 V DH 8 A D_ A 9 V DD C 8 A S_ A 8 V SD C 8 DC U2 7 A O TR 8 DC U2 6 A O TL 8 DC U1 5 A O TR 8 DC U1 4 A O TL 8 LE U1 3 I O TR N 8 LE U1 2 I O TL N 8 A S_O 1 V SL 8 Ts 0 et 7 Ts 9 et 7 Ts 8 et 7 Ts 7 et 7 AD _E 6 V D RF 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DVDD 2 VR DIG _ 1 DVSS 2 SPDIF_ IN Test Test Test Test SDIN 3 SDIN 2 SDIN 1 LRCLKIN SCLKIN VP _ 1 5 REF BGREF _ BIASREF _ AVSSADC/ EF _ R AVDDADC _ LINEIN R 10 LINEIN L 10 AVSS LI _ LINEIN9 R LINEIN9 L AVDD LI _ LINEIN8 R LINEIN8 L AVSS LI _ LINEIN7 R LINEIN7 L AVDD LI _ LINEIN6 R LINEIN6 L AVSS LI _ LINEIN5 R LINEIN5 L AVDD LI _ LINEIN4 R LINEIN4 L DESCRIPTION/ORDERING INFORMATION The TAS3208 is an audio SOC designed for digital TV Audio Systems and Mini/Micro Component applications. TAS3208 has a programmable audio DSP that preserves high-quality audio by using a 48-bit data path, 28-bit filter coefficients, and a single-cycle 28 times 48-bit multiplier. The programmability feature allows users to customize features in the DSP RAM. The TAS3208 is composed of seven functional blocks. • Clock and Serial Data Interface • Analog Input and Output • 8051 WARP Controller, Serial Control Interface and Device Control • Audio DSP – Digital Audio Processing • Power Supply • Internal References ORDERING INFORMATION TA –40°C to 85°C (1) TQFP – YZP PACKAGE (1) TBD ORDERABLE PART NUMBER TAS3208YZPR TOP-SIDE MARKING TBD Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. 2 MLI CK N DS 3 VS D DD V 3 2 _ DA IC S 2 2 _ CL IC S 2 2 _ DA IC S 1 2 _ CL IC S 1 C S GI 1 PO GI 2 PO M E / UT RE E / ST DS 4 VS D DD V 4 DS 5 VS V_ I 2 RD G A SS E D V _S LE 1 I NL NI LE 1 I NR NI A DDL V _I LE 2 I NL NI LE 2 I NR NI A SS L V _I LE 3 I NL NI LE 3 I NR NI Submit Documentation Feedback www.ti.com TAS3208 DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE SLES201A – JANUARY 2007 – REVISED FEBRUARY 2007 BLOCK DIAGRAM TBD 10 pf Rbia s 512 Fs 512Fs Rb as i OSC AVSS TBD AVSS 10 pf MCLKIN SCLKIN LRCLKIN MCLKOUT Clock Control SCLKOUT SCLKI LRCLKI SDIN 1 SDIN 2 SDIN 3 SAP IN Audio processing 2 SAP OUT SDOUT 1 LRCLKOUT MUTEZ Control SPDIF I C 2 SDA 1 SCL 1 SDA 2 SCL 2 CS GPIO 1 -4 3 1 : MUX SPDIF OUT / SDOUT 2 SPDIF IN 8051 DAC Mod HP AMP 2 2 HP OUT L /R 47 220 uF 16Ohm 10 K ohm 10 ch stereo Analog line Input 2V . 8 33K RMS 10 ch stereo Analog Inputs 1 V 2 DACOUT 2 /R L DACOUT 1L /R 0 uF . 8 A- UX M 10:1 RMS 2CH ADC 10 ch stereo 6CH DAC 2 2 Apply to all Line and DAC outputs 2. uF 2 A MUX 111 : 2 LINEOUT 1 / L R 10K ohm Line outputs DAC outputs 1V 0V . 9 RMS ( MAX ) RMS (MAX ) Submit Documentation Feedback 3 TAS3208 DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE SLES201A – JANUARY 2007 – REVISED FEBRUARY 2007 www.ti.com TYPICAL APPLICATIONS The TAS3208 may be used with an external Asynchronous Sample Rate Converter (ASRC) to accommodate asynchronous serial inputs at different sampling rates. An example of this is shown in the block diagram of Figure 2.2. TBD 10 pf Rbias 512 Fs 512Fs Rb ias OSC AVSS AVSS TBD 10 pf MCLKIN SCLKIN LRCLKIN MCLKOUT Clock Control SCLKOUT External ASRC SDIN1A SDIN2B SDIN3B SDIN4B SCLKA LRCLKA MCLKA SCLKB LRCLKB MCLKB SCLKI SCLKO LRCLKO MCLKO SDA 1 SCL1 SDA 2 SCL 2 LR LK T C OU S LK UT C O M LK T C OU CS GPIO 14 MUTEZ SCLKI MUX SDI 1 SDO 1 SDI 2 SDI 3 SDO 2 SDO 3 SDIN 1 SDIN 2 SDIN 3 LRCLKI SAP IN Audio processing 2 SAP OUT SDOUT 1 LRCLKOUT MUX LRCLKI MCLKI Control SPDIF 2 SPDIF OUT / 3 :1 MUX SDOUT 2 SPDIF IN I C 8051 DAC Mod HP AMP 2 2 HP OUT L / R 10 ch stereo Analog Inputs 2 DACOUT 2 L/ R DACOUT 1 L/ R A - UX M 10: 1 2 CH ADC 10 ch stereo 6 CH DAC 2 2 A MUX 111 : 2 LINEOUT 1 L / R Figure 1. TAS3208 and interface to external ASRC 4 Submit Documentation Feedback www.ti.com TAS3208 DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE SLES201A – JANUARY 2007 – REVISED FEBRUARY 2007 (1) ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) MIN DVDD AVDD VI Supply voltage range Supply voltage range 3.3-V TTL Input voltage range 3.3-V analog 1.8-V LVCMOS 3.3-V TTL VO Voltage range applied to any output in the high-impedance or power-off state 3.3-V analog 1.8-V LVCMOS 1.8-V LVCMOS IIK IOK Tstg Input clamp current Output clamp current Storage temperature range Lead temperature 1,6 mm (1/16 in) from case for 10 s (1) (2) (3) (4) VI < 0 or VI > DVDD VO < 0 or VO > DVDD –65 –0.5 –0.5 –0.5 –0.5 –0.5 –0.5 –0.5 –0.5 –0.5 MAX 3.8 3.8 VDDS + 0.5 AVDDS + 0.5 AVDD + 0.5 (2) VDDS + 0.5 AVDDS + 0.5 DVDD + 0.5 (3) AVDD + 0.5 (4) ±20 ±20 150 260 mA mA °C °C V V UNIT V V Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. AVDD is an internal 1.8-V supply derived from a regulator in the CXD9890Q chip. Pin XTALI is the only CXD9890Q input that is referenced to this 1.8-V logic supply. The absolute maximum rating listed is for reference; only a crystal should be connected to XTALI. DVDD is an internal 1.8-V supply derived from regulators in the CXD9890Q chip. DVDD is routed to– DVDD_BYPASS_CAP – to provide access to external filter capacitors, but should not be used to source power to external devices. Pin XTALO is the only CXD9890Q output that is derived from the internal 1.8-V logic supply AVDD. The absolute maximum rating listed is for reference; only a crystal should be connected to XTALO. AVDD is also routed to – AVDD_BYPASS_CAP – to provide access to external filter capacitors, but should not be used to source power to external devices. RECOMMENDED OPERATING CONDITIONS MIN DVDD AVDD VIH VIL TA TJ Digital supply voltage Analog supply voltage High-level input voltage Low-level input voltage 3.3-V analog 3.3-V TTL 1.8-V LVCMOS (XTL_IN) 3.3-V TTL 1.8-V LVCMOS (XTL_IN) –20 –20 25 3.0 3.0 2.0 1.26 1.95 0.8 0.54 70 105 NOM 3.3 3.3 MAX 3.6 3.6 UNIT V V V V °C °C Operating ambient air temperature (ensuring Parametric) Operating junction temperature Submit Documentation Feedback 5 TAS3208 DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE SLES201A – JANUARY 2007 – REVISED FEBRUARY 2007 www.ti.com ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER VOH High-level output voltage Low-level output voltage High-impedance output current Low-level input current High-level input current Digital supply current Analog supply current Digital supply current Analog supply