T1/E1/J1 ATM Processor

www.DataSheet4U.com Preliminary Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 1 Features s s System-on-a-chip integrated circuit supports lowspeed ATM access for next-generation wireless base transmission station (BTS), base station controller (BSC), node-B, radio network controller (RNC), and remote access concentrator (RAC) applications. IC provides an integrated octal framer that supports T1/E1/J1 formats. Supports inverse multiplexing for ATM (IMA) over selected group and link mappings ranging from four two-link groups up to one eight-link group per ATM Forum AF-PHY-0086.001. Integrates an ATM adaptation layer 2 (AAL2) segmentation and reassembly (SAR) function for support of low-speed data or voice traffic per ITU I.363.2. Provides AAL5 SAR functionality per ITU I.363.5. Provides quality of service (QoS) connection identifier (CID) multiplexing per ITU I.366.1. Enables ATM layer user network interface (UNI) or IMA mode, selectable on a per-link basis for flexible transport of delay critical voice and data traffic. Guarantees QoS for a variety of traffic types (including delay-sensitive voice, real-time data, non-real-time data, and signaling information) through an advanced hierarchical three-level priority scheduler and per-VC queueing. Supports 2032 bidirectional AAL2 CIDs. Supports 2032 bidirectional high-speed data connections or virtual circuits (VCs) via embedded context memory; filters control cells and accepts control cells via a host microprocessor interface. On-board memory is used for connection management and queue data storage. No external memory is needed. s Software package includes the following: — Device manager source code (C-based device manager ready-to-use with host RTOS). — Setup file utility to provision TAAD08JU2. — Firmware for embedded controller (executable binary). — API reference manual available for device manager software. Designed in 0.16 µm, low-power CMOS technology. s s 2 Physical s s s 3.3 V digital I/O compatibility; 1.5 V core power 520 enhanced ball-grid array (EBGA) package –40 oC to +85 oC temperature range s s s 3 Standards ITU I.363.2, ITU I.363.5, ITU I.366.1, ITU I.366.2, ITU I.432, ITU I.361, ITU I.371, ITU G.703, ITU G.704, ITU G.804, ITU G.732, ITU G.706, ITU I.610, ITU G.775, ITU G.733, ITU G.735, ITU G.965, ITU O.162, ANSI® T1.403, ANSI T1.231, ATM Forum AF-PHY-0086.001 ATM Forum AF-PHY-0039.000 ATM Forum AF-TM-0121.000 ETS 300.417-1-1 s s s s s TAAD08JU2 www.DataSheet4U.com T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Table of Contents Preliminary Data Sheet August 18, 2003 Contents 1 2 3 4 5 6 7 8 9 Page 10 11 12 13 Features ............................................................................................................................................................. 1 Physical .............................................................................................................................................................. 1 Standards ........................................................................................................................................................... 1 Description ....................................................................................................................................................... 11 Pin Definitions ..................................................................................................................................................12 Pin Description .................................................................................................................................................12 Package Pin Layout .........................................................................................................................................21 Block Diagram ..................................................................................................................................................27 Software Components ......................................................................................................................................28 9.1 Firmware.................................................................................................................................................29 9.2 Device Manager......................................................................................................................................29 9.3 Setup File Utility (SFU) ...........................................................................................................................30 9.4 TAAD08JU2 Application Code................................................................................................................31 9.5 System Software.....................................................................................................................................32 9.6 Software Development Environment ......................................................................................................32 9.7 Notes ......................................................................................................................................................33 Functional Overview.........................................................................................................................................34 10.1 Receive Direction Data Flow ..................................................................................................................34 10.1.1 PHY Layer ................................................................................................................................34 10.1.2 Low-Speed PHY Links ..............................................................................................................34 10.1.3 High-Speed PHY Links .............................................................................................................35 10.1.4 TC and IMA Layers...................................................................................................................35 10.1.5 ATM Layer ................................................................................................................................36 10.1.6 AAL Engine...............................................................................................................................36 10.1.7 Embedded Device Controller....................................................................................................37 10.2 Transmit Direction Data Flow..................................................................................................................37 10.2.1 SSCS/AAL Layer Interaction ....................................................................................................37 10.2.2 ATM Layer ................................................................................................................................37 10.2.3 IMA/TC Layer............................................................................................................................38 10.2.4 PHY Layer ................................................................................................................................38 Modes of Operation..........................................................................................................................................39 11.1 Interface Modes ......................................................................................................................................39 11.1.1 UTOPIA-2 Expansion Port Multiplexing Modes ........................................................................39 11.1.2 System Interface Port Multiplexing Modes ...............................................................................39 11.1.3 Line-Interface Modes ................................................................................................................40 11.2 Device Operating Modes ........................................................................................................................40 11.2.1 Operating Mode 1: Internal PHY Mode.....................................................................................40 11.2.2 Operating Mode 2: External PHY Mode ...................................................................................42 11.2.3 Operating Mode 3: SAR-Only Mode .........................................................................................43 11.2.4 Operating Mode Summary........................................................................................................43 Applications ......................................................................................................................................................44 12.1 BTS Network Interface Termination ........................................................................................................44 12.2 VToA Trunking Application......................................................................................................................46 12.3 Low-Speed ATM Access.........................................................................................................................47 12.4 AAL2 Cross Connect ..............................................................................................................................47 Embedded Device Controller (EDC) ................................................................................................................48 13.1 Introduction .............................................................................................................................................48 13.2 Features..................................................................................................................................................48 13.3 EDC Functional Description....................................................