DIGITAL AUDIO AMPLIFIER USING DIGITAL POWER PROCESSING

Tripath Technology, Inc. - Technical Information www.DataSheet4U.com TAA2009 STEREO 9W (8Ω) CLASS-T™ DIGITAL AUDIO AMPLIFIER USING DIGITAL POWER PROCESSING™ TECHNOLOGY TECHNICAL INFORMATION Revision 1.02 – May 2006 GENERAL DESCRIPTION The TAA2009 is a 9W/ch continuous average two-channel Class-T Digital Audio Power Amplifier IC using Tripath’s proprietary Digital Power Processing™ technology. The TAA2009, in a QFN package, along with extremely high efficiency, allows for a very compact amplifier design. Class-T amplifiers offer both the audio fidelity of Class-AB and the power efficiency of Class-D amplifiers. APPLICATIONS FEATURES LCD TV’s LCD Monitors Plasma TV’s Computer/PC Multimedia Battery Powered Systems BENEFITS Fully integrated solution with FETs Compact packaging and board design Reduced system cost with no heat sink Differential inputs minimize common-mode noise Dramatically improves efficiency versus ClassAB Signal fidelity equal to high quality linear amplifiers High dynamic range compatible with digital media such as CD, DVD, and Internet audio Capable of driving a wide range of load impedances Sophisticated pop reduction circuit TYPICAL PERFORMANCE THD+N versus Output Power 10 VDD = 12V 5 2 f = 1kHz Gain1=0, Gain0=1 BW = 22Hz - 20kHz(AES17) Class-T architecture Single Supply Operation “Audiophile” Quality Sound 0.05% THD+N @ 5W, 8Ω 0.16% IHF-IM @ 1W, 8Ω 6.4W @ 8Ω, 0.1% THD+N 3.5W @ 16Ω, 0.1% THD+N High Power 10.6W @ 6Ω, 10% THD+N 9W @ 8Ω, 10% THD+N 5W @ 16Ω, 10% THD+N Extremely High Efficiency 90% @ 5W, 16Ω 86% @ 9W, 8Ω Dynamic Range = 96 dB Mute and Sleep modes Improved turn-on & turn-off pop suppression Over-current protection with automatic restart circuit Over-temperature protection Space saving 32-pin 8mm x 8mm x 1mm QFN package with exposed pad Filterless Operation Option 32-pin QFN (Top View) IN2M C2 INL V5A BIASCAP AGND C1 IN1M THD+N (%) 1 0.5 0.2 0.1 0.05 RL = 16Ω R L = 8Ω RL = 4Ω RL = 6Ω IN1P V5D GAIN0 DGND REF SLEEP MUTE FAULT 1 2 3 4 5 6 7 8 26 27 28 29 30 31 32 11 10 9 VDD2 PGND2 OUTM2 OUTM1 PGND1 VDD1 OUTP1 25 OUTP2 24 23 22 21 20 19 18 17 IN2P AGND GAIN1 5VGEN VDDA DCAP CPUMP SUB 16 15 14 13 12 0.02 0.01 1 2 3 4 5 6 7 8 9 10 20 Output Power (W) 1 TAA2009 –KLi/1.02/ 05.06 Tripath Technology, Inc. - Technical Information www.DataSheet4U.com A B S O L U T E M A X I M U M R A T I N G S (Note 1) SYMBOL VDD MUTE, SLEEP, GAIN1, GAIN0, INL TSTORE TA ESDHB MUTE Input Voltage Storage Temperature Range Operating Free-air Temperature Range ESD Susceptibility – Human Body Model (Note 2) PARAMETER Supply Voltage (note 1) Value 14 -0.3 to V5 + 0.3 -40 to 150 -40 to +85 1500 UNITS V V °C °C V Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Please note that this is not a valid “operating condition”. The maximum voltage on the VDD pins during operation is 13.2V. Refer to the Maximum Supply Voltage section on page 13. Note 2: Human body model, 100pF discharged through a 1.5KΩ resistor. OPERATING CONDITIONS -40oC to +85OC SYMBOL VDD VIH VIL Supply Voltage (note 1) (Note 3) PARAMETER High-level Input Voltage (MUTE, SLEEP, GAIN1, GAIN0, INL) Low-level Input Voltage (MUTE, SLEEP, GAIN1, GAIN0, INL) MIN. 8.5 4.2 TYP. 12 MAX. 13.2 1.0 UNITS V V V Note 3: Recommended Operating Conditions indicate conditions for which the device is functional. See Electrical Characteristics for guaranteed specific performance limits. THERMAL CHARACTERISTICS SYMBOL θJA PARAMETER Junction-to-ambient Thermal Resistance (note 4) VALUE 21 UNITS °C/W Note 4: The θJA value is based on the exposed pad being soldered down to the printed circuit board. The exposed pad must be soldered to an exposed copper area on the printed circuit board for proper thermal and electrical performance. The exposed pad is at substrate ground. 2 TAA2009 –KLi/1.02/ 05.06 Tripath Technology, Inc. - Technical Information www.DataSheet4U.com E L E C T R I C A L C H A R A C T E R I S T I C S (Note 5) See Application/Test Circuit with single ended inputs and filtered outputs. Unless otherwise specified, VDD = 12V, f = 1kHz, Gain1=0, Gain0=1 Measurement Bandwidth = 20kHz, RL = 8Ω, TA = 25 °C, package exposed pad soldered to the printed circuit board. SYMBOL PO PARAMETER Output Power (Continuous Average/Channel) CONDITIONS THD+N = 0.1% RL = 6Ω RL = 8Ω RL = 16Ω RL = 6Ω RL = 8Ω RL = 16Ω MIN. TYP. 7.8 6.4 3.5 10.6 9 5 28 7 60 0.05 0.16 96 96 70 85 86 -10 50 4.5 0.5 160 10 MAX. UNITS W W W W W W mA mA mA % % dB dB dB dB % mV mV V V µV THD+N = 10% IDD,MUTE IDD, SLEEP Iq THD + N IHF-IM SNR CS PSRR η VOFFSET1 VOFFSET2 VOH VOL eOUT Mute Supply Current Sleep Supply Current Quiescent Current Total Harmonic Distortion Plus Noise IHF Intermodulation Distortion Signal-to-Noise Ratio Channel Separation Power Supply Rejection Ratio Power Efficiency MUTE = VIH SLEEP = VIH VIN = 0 V PO = 5W/Channel 19kHz, 20kHz, 1:1 (IHF), Po = 1W A-Weighted, POUT = 9W, RL = 8Ω f = 1 kHz 20 Hz < f < 20 kHz VDD = 9V to 13.2V POUT = 9W/Channel, RL = 8Ω Dynamic Output Offset MUTE transition from high to low Voltage (note 6) Static Output Offset Voltage MUTE = low High-level output voltage (FAULT) Low-level output voltage (FAULT) Output Noise Voltage -40°C to +85°C, IOH = 250uA -40°C to +85°C, IOL= 250uA A-Weighted, input AC grounded Note 5: Minimum and maximum limits are guaranteed but may not be 100% tested. Note 6: Refer to the Dynamic DC Offset Calibration section on page 14 for a detailed description of Dynamic Offset Voltage. 3 TAA2009 –KLi/1.02/ 05.06 Tripath Technology, Inc. - Technical Information www.DataSheet4U.com TAA2009 PINOUT 32-pin QFN (Top View) BIASCAP AGND C1 IN1M 29 30 31 32 1 2 3 4 5 6 7 8 13 12 11 10 9 IN2M C2 INL V5A 26 27 28 25 24 23 22 21 20 19 18 17 16 15 14 IN2P AGND GAIN1 5VGEN VDDA DCAP CPUMP SUB IN1P V5D GAIN0 DGND REF SLEEP MUTE FAULT VDD2 PGND2 OUTM2 OUTM1 PGND1 VDD1 OUTP1 OUTP2 4 TAA2009 –KLi/1.02/ 05.06 Tripath Technology, Inc. - Technical Information www.DataSheet4U.com PIN DESCRIPTION Pin 1, 24 2, 28 3, 22 Function IN1P, IN2P V5D, V5A GAIN0, GAIN1 Description Positive audio input for channel 1 and channel 2 Digital 5VDC, Analog 5VDC Gain select bits. GAIN0 is least significant bit. See Applications Information for programmable gain values. Both GAIN 0 and GAIN1 have internal 50KΩ pulldown resistors. Digital Ground. Connect to AGND locally (near the TAA2009). Internal reference voltage; approximately 1.0 VDC. When set to logic high, device goes into low power mode. If not used, this pin should be grounded When set to logic high, both amplifiers are muted and in idle mode. When low (grounded), both amplifiers are fully operational. If left floating, the device stays in the mute mode. This pin should be tied to GND if not used. A logic high output indicates an under-voltage condition, thermal overload, and an output is shorted to ground, or another output. Bridged output pairs Supply pins for high current H-bridges, nominally 12VDC. Power Grounds (high current) Substrate connection. Connect to PGND. Charge pump input (nominally 10V above VDDA) Charge pump switching output pin. DCAP is a free running 350kHz square wave between VDDA and DGND (12Vpp nominal). Power supply for analog VDD circuitry. Connect to same supply as VDD1 and VDD2. Regulated 5VDC source used to supply power to the input section (pins 2 and 28). Analog Ground. Connect all pins together directly at the TAA2009. Negative audio input for channel 2 and channel 1. Pop minimization capacitor. Use 10uF. Modulation selection pin. Connecting the INL pin to a logic high level enables the inductor-less mode. This mode allows the TAA2009 to be operated without an output filter as the switching outputs are in phase with zero input. If INL is tied to a logic low or left floating (pulled down via internal 50KΩ resistor to ground), the INL mode will be disabled. This results in a differential output switching pattern typical of previous Tripath generation parts such as TA2024 and TAA2008. The state of the INL pin should only be changed with MUTE at a logic high state. Input stage bias voltage (approximately 2.4VDC). 4 5 6 7 8 9, 12 16, 13 10, 15 11, 14 17 18 19 20 21 23, 30 25, 32 26, 31 27 DGND REF SLEEP MUTE FAULT OUTP1 & OUTM1 OUTP2 & OUTM2 VDD1, VDD2 PGND1, PGND2 SUB CPUMP DCAP VDDA 5VGEN AGND, AGND IN2M, IN1M C2, C1 INL 29 BIASCAP 5 TAA2009 –KLi/1.02/ 05.06 Tripath Technology, Inc. - Technical Information www.DataSheet4U.com APPLICATION / TEST CIRCUIT WITH DIFFERENTIAL INPUTS AND FILTERED OUTPUTS TAA2009 CI 1.0uF DIFFERENTIAL AUDIO INPUT CP 10uF (Pin 30) CA 1.0uF (Pin 30) 5V MUTE 7 VDD1 IN1P 1 9 OUTP1 + - Lo 10uH, 2A IN1M 32 CI 1.0uF C1 31 Processing & Modulation GAIN CONTROL PGND1 VDD1 (Pin 11) Lo 10uH, 2A Co 0.22uF CZ 0.22uF CDO 0.01uF RL 6Ω to16Ω GAIN0 3 GAIN1 22 12 OUTM1 Co 0.22uF RZ 10Ω, 1/4W BIASCAP 29 V5 PGND1 8 VDD2 CP 10uF (Pin 27) DIFFERENTIAL AUDIO INPUT CI 1.0uF FAULT C2 26 IN2P 24 16 OUTP2 + - Lo 10uH, 2A IN2M 25 CI 1.0uF (Pin 4) RREF 20.0KΩ, 1% 5 REF Processing & Modulation PGND2 VDD2 (Pin 14) Lo 10uH, 2A Co 0.22uF CZ 0.22uF CDO 0.01uF 13 OUTM2 18 CPUMP 19 DCAP Co RZ 0.22uF 10Ω, 1/4W RL 6Ω to 16Ω DCP CCP 1uF To pin 20 (VDDA) PGND2 CPUMP VDDA CD 0.1uF DCP 18 + VDD 1MΩ 20 23 21 CP 1uF CS 0.1uF CS 0.1uF To Pins 2, 28 27 INL 6 SLEEP V5D DGND V5 A AGND AGND 5VGEN N.C. 2 CS 1.0uF 4 28 VDD1 10 CSW 0.1uF + VDD CSW To Pin 21 CS 1.0uF PGND1 11 100uF, 16V 30 VDD2 15 14 CSW 0.1uF + 17 SUB CSW PGND2 100uF, 16V Note: Analog and Digital/Power Grounds must be connected locally at the TAA2009 Analog Ground Power Ground 6 TAA2009 –KLi/1.02/ 05.06 Tripath Technology, Inc. - Technical Information www.DataSheet4U.com APPLICATION / TEST CIRCUIT WITH SINGLE ENDED INPUTS AND FILTERED OUTPUTS TAA2009 CI 1.0uF SINGLE ENDED AUDIO INPUT