(T6819 / T6829) Dual Triple DMOS Output Driver

Features • • • • • • • • • • • • • • Supply Voltage up to 40 V RDSon Typically 0.5 Ω at 25°C, Maximum 1 Ω at 150°C Up to 1.5 A Output Current Three High-side and Three Low-side Drivers Usable as Single Outputs or Half Bridges Capable to Switch all Kinds of Loads such as DC Motors, Bulbs, Resistors, Capacitors and Inductors PWM Capability for Each Output Controlled by External PWM Signal No Shoot-through Current Very Low Quiescent Current IS < 5 µA in Standby Mode over Total Temperature Range Outputs Short-circuit Protected Selective Overtemperature Protection for Each Switch and Overtemperature Prewarning Undervoltage Protection Various Diagnostic Functions such as Shorted Output, Open Load, Overtemperature and Power-supply Fail Detection Serial Data Interface, Daisy Chain Capable, up to 2 MHz Clock Frequency SO16 Power Package Dual Triple DMOS Output Driver with Serial Input Control T6819/T6829 Preliminary Description The T6819/T6829 are fully protected driver interfaces designed in 0.8 µm BCDMOS technology. They are used to control up to six different loads by a microcontroller in automotive and industrial applications. Each of the three high-side and three low-side drivers is capable to drive currents up to 1.5 A. Each driver is freely configurable and can be controlled separately from a standard serial data interface. Therefore, all kinds of loads such as bulbs, resistors, www.DataSheet4U.com capacitors and inductors can be combined. The IC design especially supports the applications of H-bridges to drive DC motors. The capability to control each output with an external PWM signal opens additional applications. Protection is guaranteed regarding short-circuit conditions, overtemperature and undervoltage. Various diagnostic functions and a very low quiescent current in stand-by mode opens a wide range of applications. Automotive qualification (protection against conducted interferences, EMC protection and 2-kV ESD protection) gives added value and enhanced quality for exacting requirements of automotive applications. Rev. 4531A–BCD–10/02 1 Figure 1. Block Diagram OUT3H 4 OUT2H 14 OUT1H 13 Fault detect Fault detect Fault detect Charge pump 12 6 DI Vs 7 CLK S I O C S O L D P H 3 P L 3 P H 2 P L 2 P H 1 P L 1 H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 S R R 5 Input register Output register P S F I N H O V L n. u. n. u. n. n. u. u. Serial interface n. n. u. u. H S 3 L S 3 H S 2 L S 2 H S 1 LT SP 1 Control logic UV protection Power-on reset 11 CS Vcc 10 DO 16 PWM 8 Fault detect Fault detect Fault detect GND Thermal protection 9 GND GND 1 3 15 2 OUT3L OUT2L OUT1L 2 T6819/T6829 4531A–BCD–10/02 T6819/T6829 Pin Configuration Figure 2. Pinning SO16 GND OUT1L OUT3L OUT3H CS DI CLK PWM 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 GND OUT2L OUT2H OUT1H VS VCC DO GND Pin Description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol GND OUT1L OUT3L OUT3H CS DI CLK PWM GND DO VCC VS OUT1H OUT2H OUT2L GND Function T6819: ground; reference potential; internal connection to Pin 9 and Pin 16; cooling tab T6829: Additional connection to heat slug Low-side driver output 1; Power-MOS open drain with internal reverse diode; short-circuit protection; overtemperature protection; diagnosis for short and open load; PWM ability Low-side driver output 3; see Pin 2 High-side driver output 3; power MOS open source with internal reverse diode; short-circuit protection; overtemperature protection; diagnosis for short and open load; PWM ability Chip select input; 5-V CMOS logic level input with internal pull up; low = serial communication is enabled, high = disabled Serial data input; 5-V CMOS logic level input with internal pull down; receives serial data from the control device; DI expects a 16-bit control word with LSB being transferred first Serial clock input; 5-V CMOS logic level input with internal pull down; controls serial data input interface and internal shift register (fmax = 2 MHz) PWM input; 5-V CMOS logic level input with internal pull down; receives PWM signal to control outputs which are selected for PWM mode by the serial data interface, high = outputs on, low = outputs off Ground; see Pin 1 Serial data output; 5-V CMOS logic-level tristate output for output (status) register data; sends 16-bit status information to the microcontroller (LSB is transferred first); output will remain tristated unless device is selected by CS = low, therefore, several ICs can operate on one data-output line only. Logic supply voltage (5 V) Power supply for high-side output stages OUT1H, OUT2H, OUT3H, internal supply High-side driver output 1; see PIN 4 High-side driver output 2; see PIN 4 Low-side driver output 2; see Pin 2 Ground; see Pin 1 3 4531A–BCD–10/02 Functional Description Serial Interface Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be transferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS is high, Pin DO is in tristate condition. This output is enabled on the falling edge of CS. Output data will change their state with the rising edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP) is transferred first. Figure 3. Data Transfer CS DI SRR 0 LS1 1 HS1 2 LS2 3 HS2 4 LS3 5 HS3 6 PL1 7 PH1 8 PL2 9 PH2 10 PL3 11 PH3 12 OLD 13 OCS 14 SI 15 CLK DO TP S1L S1H S2L S2H S3L S3H n. u. n. u. n. u. n. u. n. u. n. u. OVL INH PSF Input Data Protocol Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Input Register SRR LS1 HS1 LS2 HS2 LS3 HS3 PL1 PH1 PL2 PH2 PL3 PH3 OLD OCS SI Function Status register reset (high = reset; the bits PSF and OVL in the output data register are set to low) Controls output LS1 (high = switch output LS1 on) Controls output HS1 (high = switch output HS1 on) See LS1 See HS1 See LS1 See HS1 Output LS1 additionally controlled by PWM Input Output HS1 additionally controlled by PWM Input See PL1 See PH1 See PL1 See PH1 Open load detection (low = on) Overcurrent shutdown (high = overcurrent shutdown is active) Software inhibit; low = standby, high = normal operation (data transfer is not affected by standby function because the digital part is still powered) 4 T6819/T6829 4531A–BCD–10/02 T6819/T6829 Output Data Protocol Bit 0 Output (Status) Register TP Function Temperature prewarning: high = warning Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off); not affected by SRR Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off); not affected by SRR Description see LS1 Description see HS1 Description see LS1 Description see HS1 Not used Not used Not used Not used Not used Not used Over-load detected: set high, when at least one output is switched off by a short-circuit condition or an overtemperature event. Bits 1 to 6 can be used to detect the affected switch. (open-load detection bit OLD = high) Inhibit: this bit is controlled by software (bit SI in input register) High = standby, low = normal operation Power-supply fail: undervoltage at Pin VS detected 1 Status LS1 2 Status HS1 3 4 5 6 7 8 9 10 11 12 Status LS2 Status HS2 Status LS3 Status HS3 n. u. n. u. n. u. n. u. n. u. n. u. 13 OVL 14 15 INH PSF After power-on reset, the input register has the following status Bit 15 SI Bit 14 OCS Bit 13 OLD Bit 12 PH3 Bit 11 PL3 Bit 10 PH2 Bit 9 PL2 Bit 8 PH1 Bit 7 PL1 Bit 6 HS3 Bit 5 LS3 Bit 4 HS2 Bit 3 LS2 Bit 2 HS1 Bit 1 LS1 Bit 0 SRR H H H L L L L L L L L L L L L L The following patterns are used to enable internal test modes of the IC. It is not recommended to use these patterns during normal operation. Bit 15 Bit 14 Bit 13 (OCS) Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 (HS3) Bit 5 (LS3) Bit 4 (HS2) Bit 3 (LS2) Bit 2 (HS1) Bit 1 (LS1) Bit 0 (SRR) H H H H H H H H H H L L H L L L H L L H L L L H L L H L L L L L L L L L L L L L L L L L L L L L 5 4531A–BCD–10/02 Power-supply Fail In case of undervoltage at Pin VS, the Power-Supply Fail bit (PSF) in the output register is set and all outputs are disabled. To detect an undervoltage, its duration has to last longer than the undervoltage detection delay time tdUV. The outputs are enabled immediately when supply voltage recovers normal operation value. The PSF bit stays high until it is reset by the SRR bit in the input register. If the open-load detection bit (OLD) is set to low, a pull-up current for each high-side switch and a pull-down current for each low-side switch is turned on (open-load detection current IOUT1-3). If the current through the external load does not reach the openload detection current, the corresponding bit of the output in the output register is set to high. Switching on an output stage with OLD bit set to low disables the open-load function for this output. Open-load Detection Overtemperature Protection If the junction temperature of one ore more output stages exceeds the thermal prewarning threshold, TjPW set, the temperature prewarning bit (TP) in the output register is set. When the temperature falls below the thermal prewarning threshold, TjPW reset, the Bit TP is reset. The TP bit can be read without transferring a complete 16-bit data word. The status of TP is available at Pin DO with the falling edge of CS. After the microcontroller has read this information, CS is set high and the data transfer is interrupted without affecting the status of input and output registers. If the junction temperature of an output stage exceeds the thermal shutdown threshold, Tj switch off, the affected ou