(T6818 / T6828) Triple Halfbridge DMOS OUTPUT DRIVER

Features • • • • • • • • • • • • • Supply Voltage up to 40 V RDSon Typically 0.5 Ω at 25°C, Maximum 1.1 Ω at 150°C Up to 1.5 A Output Current Three Half-bridge Outputs Formed by Three High-side and Three Low-side Drivers Capable to Switch all Kinds of Loads Such as DC Motors, Bulbs, Resistors, Capacitors and Inductors No Shoot-through Current Very Low Quiescent Current IS < 5 µA in Standby Mode versus Total Temperature Range Outputs Short-circuit Protected Overtemperature Protection for Each Switch and Overtemperature Prewarning Undervoltage Protection Various Diagnostic Functions Such as Shorted Output, Open-load, Overtemperature and Power-supply Fail Detection Serial Data Interface, Daisy Chain Capable, up to 2 MHz Clock Frequency SO14 Power Package Description The T6818/T6828 are fully protected driver interfaces designed in 0.8-µm BCDMOS technology. They are used to control up to 3 different loads by a microcontroller in automotive and industrial applications. Each of the 3 high-side and 3 low-side drivers is capable to drive currents up to 1.5 A. The drivers are internally connected to form 3 half-bridges and can be controlled separately from a standard serial data interface. Therefore, all kinds of loads such as bulbs, resistors, capacitors and inductors can be combined. The IC design especially supports the application of H-bridges to drive DC motors. www.DataSheet4U.com Protection is guaranteed regarding short-circuit conditions, overtemperature and under voltage. Various diagnostic functions and a ver y low quiescent current in stand-by-mode opens a wide range of applications. Automotive qualification (protection against conducted interferences, EMC protection and 2-kV ESD protection) gives added value and enhanced quality for exacting requirements of automotive applications. Triple Halfbridge DMOS Output Driver with Serial Input Control T6818/T6828 Rev. 4530E–BCD–07/04 Figure 1. Block Diagram n. u. n. u. O C S n. u. n. u. n. u. n. u. n. u. n. u. H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 S R R 3 VS Input register Output register DI 5 P S F O P L S C D n. u. n. u. n. u. n. u. n. u. n. u. H S 3 Serial interface L S 3 H S 2 L S 2 H S 1 L S 1 T P Charge pump CLK 6 CS 4 Fault detect INH 10 Fault detect Fault detect UV protection 11 Control logic VCC DO 9 Power-on reset 1 7 GND GND GND GND Fault detect Fault detect Fault detect Thermal protection 13 OUT1 8 14 2 OUT3 12 OUT2 2 T6818/T6828 4530E–BCD–07/04 T6818/T6828 Pin Configuration Figure 2. Pining SO14 GND OUT3 VS CS DI CLK GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 GND OUT1 OUT2 VCC INH DO GND Pin Description Pin 1 Symbol GND Function T6818: ground; reference potential; internal connection to pin 7, 8 and 14; cooling tab T6828: additional connection to heat slug Half-bridge output 3; formed by internally connected power MOS high-side switch 3 and low-side switch 3 with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and open load Power supply for output stages OUT1, OUT2 and OUT3, internal supply Chip select input; 5-V CMOS logic level input with internal pull up; low = serial communication is enabled, high = disabled Serial data input; 5-V CMOS logic level input with internal pull down; receives serial data from the control device; DI expects a 16-bit control word with LSB being transferred first Serial clock input; 5-V CMOS logic level input with internal pull down; controls serial data input interface and internal shift register (fmax = 2 MHz) Ground; see pin 1 Ground; see pin 1 Serial data output; 5-V CMOS logic level tri-state output for output (status) register data; sends 16-bit status information to the microcontroller (LSB is transferred first); output will remain tri-stated unless device is selected by CS = low, therefore, several ICs can operate on one data output line only. Inhibit input; 5-V logic input with internal pull down; low = standby, high = normal operation Logic supply voltage (5 V) Half-bridge output 2; see pin 2 Half-bridge output 1; see pin 2 Ground; see pin 1 2 3 4 5 6 7 8 9 OUT3 VS CS DI CLK GND GND DO 10 11 12 13 14 INH VCC OUT2 OUT1 GND 3 4530E–BCD–07/04 Functional Description Serial Interface Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be transferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS is high, pin DO is in tri-state condition. This output is enabled on the falling edge of CS. Output data will change their state with the rising edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP) is transferred first. Figure 3. Data Transfer CS DI SRR LS1 HS1 LS2 HS2 LS3 HS3 n. u. n. u. n. u. n. u. n. u. n. u. OCS n. u. n. u. 0 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DO TP S1L S1H S2L S2H S3L S3H n. u. n. u. n. u. n. u. n. u. n. u. SCD OPL PSF Table 1. Input Data Protocol Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Input Register SRR LS1 HS1 LS2 HS2 LS3 HS3 n. u. n. u. n. u. n. u. n. u. n. u. OCS n. u. n. u. Function Status register reset (high = reset; the bits PSF, OPL and SCD in the output data register are set to low) Controls output LS1 (high = switch output LS1 on) Controls output HS1 (high = switch output HS1 on) See LS1 See HS1 See LS1 See HS1 Not used Not used Not used Not used Not used Not used Overcurrent shutdown (high = overcurrent shutdown is active) Not used Not used 4 T6818/T6828 4530E–BCD–07/04 T6818/T6828 Table 2. Output Data Protocol Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 Output (Status) Register TP Status LS1 Status HS1 Status LS2 Status HS2 Status LS3 Status HS3 n. u. n. u. n. u. n. u. n. u. n. u. SCD Function Temperature prewarning: high = warning High = output is on, low = output is off; not affected by SRR High = output is on, low = output is off; not affected by SRR Description see LS1 Description see HS1 Description see LS1 Description see HS1 Not used Not used Not used Not used Not used Not used Short circuit detected: set high when at least one high-side or low-side switch is switched off by a short-circuit condition. Bits 1 to 6 can be used to detect the shorted switch. Open load detected: set high, when at least one active high-side or low-side switch sinks/sources a current below the open load threshold current. Power-supply fail: undervoltage at pin VS detected 14 15 OPL PSF After power-on reset, the input register has the following status: Bit 15 x Bit 14 x Bit 13 (OCS) H x x x x x x Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 (HS3) L Bit 5 (LS3) L Bit 4 (HS2) L Bit 3 (LS2) L Bit 2 (HS1) L Bit 1 (LS1) L Bit 0 (SRR) L The following patterns are used to enable internal test modes of the IC. It is not recommended to use these patterns during normal operation. Bit 15 H H H Bit 14 H H H Bit 13 (OCS) H H H H L L H L L L H L L H L L L H L L H Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 (HS3) L L L Bit 5 (LS3) L L L Bit 4 (HS2) L L L Bit 3 (LS2) L L L Bit 2 (HS1) L L L Bit 1 (LS1) L L L Bit 0 (SRR) L L L 5 4530E–BCD–07/04 Power-supply Fail In case of undervoltage at pin VS, the Power-Supply Fail bit (PSF) in the output register is set and all outputs are disabled. To detect an undervoltage, its duration has to last longer than the undervoltage detection delay time tdUV. The outputs are enabled immediately when supply voltage recovers normal operation value. The PSF bit stays high until it is reset by the SRR bit in the input register. If the current through a high-side or low-side switch in ON-state stays below the openload detection threshold, the open-load detection bit (OPL) in the output register is set. The OPL bit stays high until it is reset by the SRR bit in the input register. To detect an open load, its duration has to last longer than the open-load detection delay time tdSd. Open-load Detection Overtemperature Protection If the junction temperature of one or more output stages exceeds the thermal prewarning threshold, TjPW set, the temperature prewarning bit (TP) in the output register is set. When the temperature falls below the thermal prewarning threshold, TjPW reset, the bit TP is reset. The TP bit can be read without transferring a complete 16-bit data word. The status of TP is available at pin DO with the falling edge of CS. After the microcontroller has read this information, CS is set high and the data transfer is interrupted without affecting the status of input and output registers. If the junction temperature of one or more output stages exceeds the thermal shutdown threshold, Tj switch off, all outputs are disabled and the corresponding bits in the output register are set to low. The outputs can be enabled again when the temperature falls below the thermal shutdown threshold, Tjswitch on and the SRR bit in the input register is set to high. Hysteresis of thermal prewarning and shutdown threshold avoids oscillations. Short-circuit Protection The output currents are limited by a current regulator. Overcurrent detection is activated by writing a high to the OCS bit in the input register. When the current in an output stage exceeds the overcurrent limitation and shutdown threshold, it is switched off after a delay time (tdSd). The short-circuit detection bit (SCD) is set and the corresponding status bit in the output register is set to low. For OCS = low the overcurrent shutdown is inactive. The SCD bit is also set if the current exceeds the overcurrent limitation and shutdown threshold, but the outputs are not affected. By writing a high to the SRR bit in the input register the SCD bit is reset and the disabled outputs are enabled. 0 V applied to pin 10 (INH) inhibits the T6818/T6828. All output switches are then turned off and switched to tri-state. The data in the