Dual Hex Output Driver

Features • Six High-side and Six Low-side Drivers • Outputs Freely Configurable as Switch, Half Bridge or H-bridge • Capable to Switch all Kinds of Loads such as DC Motors, Bulbs, Resistors, Capacitors • • • • • • • • • • • • and Inductors 0.6A Continuous Current per Switch Low-side: RDSon < 1.5Ω versus Total Temperature Range High-side: RDSon < 2.0Ω versus Total Temperature Range Very Low Quiescent Current Is < 20 µA in Standby Mode Outputs Short-circuit Protected Overtemperature Prewarning and Protection Undervoltage Protection Various Diagnosis Functions such as Shorted Output, Open Load, Overtemperature and Power Supply Fail Serial Data Interface Operation Voltage up to 40V Daisy Chaining Possible SO28 Power Package 40-V Dual Hex Output Driver with Serial Input Control T6816 1. Description The T6816 is a fully protected driver interface designed in 0.8 µm BCDMOS technolwww.DataSheet4U.com ogy. It is especially suitable for truck or bus applications and the industrial 24-V supply. It controls up to 12 different loads via a 16-bit dataword. Each of the six high-side and six low-side drivers is capable to drive currents up to 600 mA. The drivers are freely configurable and can be controlled separately from a standard serial data interface. Therefore, all kinds of loads such as bulbs, resistors, capacitors and inductors can be combined. The IC is also designed to easily build H-bridges to drive DC motors in motion-control applications. Protection is guaranteed in terms of short-circuit conditions, overtemperature and undervoltage. Various diagnosis functions and a very low quiescent current in standby mode open a wide range of applications. Automotive qualification referring to conducted interferences, EMC protection and 2 kV ESD protection gives added value and enhanced quality for the exacting requirements of automotive applications. Rev. 4595E–BCD–09/05 Figure 1-1. Block Diagram HS1 15 HS2 15 13 HS3 13 12 HS4 12 HS5 3 3 HS6 2 2 28 28 Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect 5 VS VS GND 10 DI 26 6 Osc CLK 25 S I S C T O L D H S 6 L S 6 H S 5 L S 5 H S 4 L S 4 H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 S R R 7 GND VS CS 24 Input Register Output Register P S F I N H S C D H S 6 L S 6 H S 5 L S 5 H S 4 L S 4 H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 T P Control logic 8 UV protection Thermal protection Power-on reset GND 9 GND INH 17 20 GND 18 DO 21 GND VCC Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect 22 GND 23 GND VCC 19 VCC 16 14 11 4 1 27 LS1 LS2 LS3 LS4 LS5 LS6 2 T6816 4595E–BCD–09/05 T6816 2. Pin Configuration Figure 2-1. Pinning SO28 HS6 28 LS6 27 DI 26 CLK 25 CS 24 GND GND GND GND VCC DO 23 22 21 20 19 18 INH 17 LS1 HS1 16 15 T6816 Lead frame 1 LS5 2 HS5 3 HS4 4 LS4 5 VS 6 7 8 9 10 VS 11 LS3 12 HS3 13 HS2 14 LS2 GND GND GND GND Table 2-1. Pin 1 2 3 4 5 6, 7, 8, 9 10 11 12 13 14 15 16 17 18 19 20-23 24 25 26 27 28 Pin Description Symbol LS5 HS5 HS4 LS4 VS GND VS LS3 HS3 HS2 LS2 HS1 LS1 INH DO VCC GND CS CLK DI LS6 HS6 Function Low-side driver output 5; Power-MOS open drain with internal reverse diode; short-circuit protection; diagnosis for short and open load High-side driver output 5; Power-MOS open drain with internal reverse diode; short-circuit protection; diagnosis for short and open load High-side driver output 4; see pin 2 Low-side driver output 4; see pin 1 Power supply output stages HS4, HS5, HS6, internal supply; external connection to pin 10 necessary Ground; reference potential; internal connection to pin 20-23; cooling tab Power supply output stages HS1, HS2 and HS3 Low-side driver output 3; see pin 1 High-side driver output 3; see pin 2 High-side driver output 2; see pin 2 Low-side driver output 2; see pin 1 High-side driver output 1; see pin 2 Low-side driver output 1; see pin 1 Inhibit input; 5V logic input with internal pull down; low = standby, high = normal operating Serial data output; 5V CMOS logic level tri-state output for output (status) register data; sends 16-bit status information to the microcontroller (LSB is transferred first). Output will remain tri-stated unless device is selected by CS = low, therefore, several ICs can operate on one data output line only. Logic supply voltage (5V) Ground; see pin 6-9 Chip select input; 5V CMOS logic level input with internal pull up; low = serial communication is enabled, high = disabled Serial clock input; 5V CMOS logic level input with internal pull down; controls serial data input interface and internal shift register (fmax = 2 MHz) Serial data input; 5V CMOS logic level input with internal pull down; receives serial data from the control device; DI expects a 16-bit control word with LSB being transferred first Low-side driver output 6; see pin 1 High-side driver output 6; see pin 2 3 4595E–BCD–09/05 3. Functional Description 3.1 Serial Interface Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be transferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS is high, pin DO is in tri-state condition. This output is enabled on the falling edge of CS. Output data will change their state with the rising edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP) is transferred first. Figure 3-1. CS Data Transfer Input Data Protocol DI SRR 0 LS1 1 HS1 2 LS2 3 HS2 4 LS3 5 HS3 6 LS4 7 HS4 8 LS5 9 HS5 10 LS6 11 HS6 12 OLD 13 SCT 14 SI 15 CLK DO TP SLS1 SHS1 SLS2 SHS2 SLS3 SHS3 SLS4 SHS4 SLS5 SHS5 SLS6 SHS6 SCD INH PSF Table 3-1. Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Input Data Protocol Input Register SRR LS1 HS1 LS2 HS2 LS3 HS3 LS4 HS4 LS5 HS5 LS6 HS6 OLD SCT Function Status register reset (high = reset; the bits PSF, SCD and overtemperature shutdown in the output data register are set to low) Controls output LS1 (high = switch output LS1 on) Controls output HS1 (high = switch output HS1 on) See LS1 See HS1 See LS1 See HS1 See LS1 See HS1 See LS1 See HS1 See LS1 See HS1 Open load detection (low = on) Programmable time delay for short circuit (shutdown delay high/low = 12 ms/1.5 ms) Software inhibit; low = standby, high = normal operation (data transfer is not affected by standby function because the digital part is still powered) 15 SI 4 T6816 4595E–BCD–09/05 T6816 Table 3-2. Bit 0 Output Data Protocol Output (Status) Register Function TP Temperature prewarning: high = warning (overtemperature shutdown see remark below) Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off) Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off) Description see LS1 Description see HS1 Description see LS1 Description see HS1 Description see LS1 Description see HS1 Description see LS1 Description see HS1 Description see LS1 Description see HS1 Short circuit detected: set high, when at least one output is switched off by a short circuit condition Inhibit: this bit is controlled by software (bit SI in input register) and hardware inhibit (pin 17). High = standby, low = normal operation Power supply fail: undervoltage at pin VS detected 1 Status LS1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Note: Status HS1 Status LS2 Status HS2 Status LS3 Status HS3 Status LS4 Status HS4 Status LS5 Status HS5 Status LS6 Status HS6 SCD INH PSF Bit 0 to 15 = high: overtemperature shutdown Table 3-3. Bit 15 (SI) H Bit 14 (SCT) H Status of the Input Register after Power on Reset Bit 13 (OLD) H Bit 12 (HS6) L Bit 11 (LS6) L Bit 10 (HS5) L Bit 9 (LS5) L Bit 8 (HS4) L Bit 7 (LS4) L Bit 6 (HS3) L Bit 5 (LS3) L Bit 4 (HS2) L Bit 3 (LS2) L Bit 2 (HS1) L Bit 1 (LS1) L Bit 0 (SRR) L 5 4595E–BCD–09/05 3.2 Power Supply Fail In case of undervoltage at pin VS, an internal timer is started. When the undervoltage delay time (tdUV) programmed by the SCT bit is reached, the power supply fail bit (PSF) in the output register is set and all outputs are disabled. When normal voltage is present again, the outputs are enabled immediately. The PSF bit remains high until it is reset by the SRR bit in the input register. 3.3 Open-load Detection If the open-load detection bit (OLD) is set to low, a pull-up current for each high-side switch and a pull-down current for each low-side switch is turned on (open-load detection current IHS1-6, ILS1-6). If VVS – VHS1-6 or VLS1-6 is lower than the open-load detection threshold (open-load condition), the corresponding bit of the output in the output register is set to high. Switching on an output stage with OLD bit set to low disables the open-load function for this output. 3.4 Overtemperature Protection If the junction temperature exceeds the thermal prewarning threshold, TjPW set, the temperature prewarning bit (TP) in the output register is set. When the temperature falls below the thermal prewarning threshold, TjPW reset, the bit TP is reset. The TP bit can be read without transferring a complete 16-bit data word: with CS = high to low, the state of TP appears at pin DO. After the microcontroller has read this information, CS is set high and the data transfer is interrupted without affecting the state of the input and output registers. If the junction temperature exceeds the thermal shutdown threshold, Tj switch off, the outputs are disabled and all bits in the output register are set high. The outputs can be enabled again when the temperature falls below the thermal shutdown threshold, Tj switch on, and when a high has been written to the SRR bit in the input regis