SONET/SDH PRECISION CLOCK MULTIPLIER IC

Si5321 SONET/SDH P R E C I S I O N C L O C K M U L T I P L I E R I C Features Ultra-low jitter clock output with jitter generation as low as 0.3 psRMS No external components (other than a resistor and bypassing) Input clock ranges at 19, 39, 78, 155, 311, or 622 MHz Output clock ranges at 19, 39, 78, 155, 311, 622, 1244, or 2488 MHz Maximum range includes 693 MHz for 10 GbE FEC support Digital hold for loss-of-input clock Support for 255/238 (15/14), 255/237 (85/79), and 66/64 FEC scaling (ITU-T G.709 and IEEE 802.3ae) Selectable loop bandwidth Loss-of-signal alarm output Low power Small size (9x9 mm) Backwards compatible with Si5320 Si5321 Si5321 Applications SONET/SDH line/port cards Terabit routers Core switches Digital cross connects Ordering Information: See page 30. Description The Si5321 is a precision clock multiplier that exceeds the requirements of high-speed communication systems, including OC-192/OC-48 and 10 Gigabit Ethernet. This device phase locks to an input clock in the 19, 39, 78, 155, 311 or 622 MHz frequency range and generates a frequency-multiplied clock output that can be configured for operation www.DataSheet4U.com in the 19, 39, 78, 155, 622, 1244, or 2488 MHz frequency range. Silicon Laboratories DSPLL™ technology provides PLL functionality with unparalleled performance. It eliminates external loop filter components, provides programmable loop parameters, and simplifies design. FEC rates are supported by selectable forward and reverse 255/ 238 (15/14), 255/237 (85/79), and 66/64 (33/32) conversion factors. The ITU-T G.709 255/237 rate and the IEEE 802.3ae 66/64 rate are supported when using a 155 MHz or higher rate input clock. The performance and integration of Silicon Laboratories’ Si5321 clock IC provides high-level support of the latest specifications and systems. It operates from a single 3.3 V supply. Functional Block Diagram REXT VSEL33 V DD GND Biasing & Supply Regulation FXDDELAY CLKIN+ CLKIN– 2 CAL_ACTV ÷ Signal Detect 3 2 DSPLL™ DH_ACTV ÷ 2 Calibration CLKOUT+ CLKOUT– FRQSEL[2:0] RSTN/CAL VALTIME LOS 2 BWBOOST BWSEL[1:0] INFRQSEL[2:0] FEC[2:0] Rev. 2.3 4/05 Copyright © 2005 by Silicon Laboratories Si5321 Si5321 2 Rev. 2.3 Si5321 TABLE O F CONTENTS SECTION PAGE 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.1. DSPLL™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 2.2. Clock Input and Output Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 2.3. PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4. Loss-of-Signal Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 2.5. Digital Hold of the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.6. Hitless Recovery from Digital Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 2.7. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.8. PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.9. Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 2.10. Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.11. Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.12. Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.13. Design and Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3. Pin Descriptions: Si5321 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6. 9x9 mm CBGA Card Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Rev. 2.3 3 Si5321 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Ambient Temperature Si5321 Supply Voltage3, 3.3 V Supply Symbol TA VDD33 Test Condition Min1 –202 3.135 Typ 25 3.3 Max1 85 3.465 Unit °C V Notes: 1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. 2. The Si5321 is guaranteed by design to operate at –40° C. All electrical specifications are guaranteed for an ambient temperature of –20 to 85° C. 3. The Si5321 specifications are guaranteed when using the recommended application circuit (including component tolerance) of Figure 5 on page 16. 4 Rev. 2.3 Si5321 C LKIN + C LKIN – V IS A. O peration with Single-Ended C lock Input* N ote: W hen using single-ended clock sources, the unused clock input on the Si5321 m ust be ac-coupled to ground. C LKIN + C LKIN – 0.5 V ID (C LKIN+) – (C LKIN –) V ID B. O peration with D ifferential C lock Input N ote: Transm ission line term ination, when required, m ust be provided externally. Figure 1. CLKIN Voltage Characteristics 80% 20% tF tR Figure 2. Rise/Fall Time Measurement (C L K IN + ) - (C L K IN - ) 0V tL O S Figure 3. Transitionless Period on CLKIN for Detecting a LOS Condition Rev. 2.3 5 Si5321 Table 2. DC Characteristics, VDD = 3.3 V (VDD33 = 3.3 V ±5%, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Supply Current 1 Supply Current 2 Power Dissipation Using 3.3 V Supply Clock Output Common Mode Input (CLKIN) Voltage1,2,3 IDD IDD PD VICM VIS VID RIN VOD VOCM ISC(–) ISC(+) VIL VIH IIL IIH Ipd RIN VOL VOH 622.08 MHz In, 19.44 MHz Out 19.44 MHz In, 622.08 MHz Out 19.44 MHz In, 622.08 MHz Out — — — 141 135 155 145 mA mA 445 1.0 1.5 — — 80 825 1.8 — 15 — — — — — — — — 479 2.0 5004 5004 — 1100 2.2 — — 0.8 — 50 50 50 — 0.4 — mW V mVPP mVPP kΩ mVPP V mA mA V V µA µA µA Single-Ended Input Voltage2,3,4 (CLKIN) Differential Input Voltage Swing2,3,4 (CLKIN) Input Impedance (CLKIN+, CLKIN–) Differential Output Voltage Swing (CLKOUT) Output Common Mode Voltage (CLKOUT) Output Short to GND (CLKOUT) Output Short to VDD25 (CLKOUT) Input Voltage Low (LVTTL Inputs) Input Voltage High (LVTTL Inputs) Input Low Current (LVTTL Inputs) Input High Current (LVTTL Inputs) Internal Pulldowns (LVTTL Inputs) Input Impedance (LVTTL Inputs) Output Voltage Low (LVTTL Outputs) Output Voltage High (LVTTL Outputs) Notes: See Figure 1A See Figure 1B 200 200 — 100 Ω Load Line-to-Line 100 Ω Load Line-to-Line 750 1.4 –60 — — 2.0 — — — 50 kΩ V V IO = 0.5 mA IO = 0.5 mA — 2.0 1. The Si5321 device provides weak 1.5 V internal biasing that enables ac-coupled operation. 2. Clock inputs may be driven differentially or single-endedly. When driven single-endedly, the unused input should be accoupled to ground. 3. Transmission line termination, when required, must be provided externally. 4. Although the Si5321 device can operate with input clock swings as high as 1500 mVPP, Silicon Laboratories recommends maintaining the input clock amplitude below 500 mVPP for optimal performance. 6 Rev. 2.3 Si5321 Table 3. AC Characteristics (VDD33 = 3.3 V ±5%, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Input Clock Frequency (CLKIN) FEC[2:0] = 000 (non FEC) INFRQSEL[2:0] = 001 INFRQSEL[2:0] = 010 INFRQSEL[2:0] = 011 INFRQSEL[2:0] = 100 INFRQSEL[2:0] = 101 INFRQSEL[2:0] = 110 Input Clock Frequency (CLKIN) FEC[2:0] = 001 (forward FEC) INFRQSEL[2:0] = 001 INFRQSEL[2:0] = 010 INFRQSEL[2:0] = 011 INFRQSEL[2:0] = 100 INFRQSEL[2:0] = 101 INFRQSEL[2:0] = 110 Input Clock Frequency (CLKIN) FEC[2:0] = 010 (reverse FEC) INFRQSEL[2:0] = 001 INFRQSEL[2:0] = 010 INFRQSEL[2:0] = 011 INFRQSEL[2:0] = 100 INFRQSEL[2:0] = 101 INFRQSEL[2:0] = 110 Input Clock Frequency (CLKIN) FEC[2:0] = 100 (forward FEC) INFRQSEL[2:0] = 001 INFRQSEL[2:0] = 010 INFRQSEL[2:0] = 011 INFRQSEL[2:0] = 100 INFRQSEL[2:0] = 101 INFRQSEL[2:0] = 110 Input Clock Frequency (CLKIN) FEC[2:0] = 101 (reverse FEC) INFRQSEL[2:0] = 001 INFRQSEL[2:0] = 010 INFRQSEL[2:0] = 011 INFRQSEL[2:0] = 100 INFRQSEL[2:0] = 101 INFRQSEL[2:0] = 110 fCLKIN No FEC Scaling 19.436 38.872 77.744 155.48 310.97 621.95 — — — — — — 21.685 43.369 86.738 173.48 346.95 693.90 MHz fCLKIN 255/238 FEC Scaling 18.142 36.284 72.568 145.13 290.27 580.54 — — — — — — 20.239 40.478 80.955 161.91 323.82 647.64 MHz fCLKIN 238/255 FEC Scaling 20.826 41.652 83.305 166.61 333.22 666.44 — — — — — — 23.234 46.465 92.934 185.87 371.74 743.47 MHz fCLKIN 255/237 FEC Scaling Minimum input frequency is in the 155 MHz range N/A N/A N/A 144.52 289.05 578.11 N/A N/A N/A — — — N/A N/A N/A 161.23 322.46 644.92 MHz fCLKIN 237/255 FEC Scaling Minimum input frequency is in the 155 MHz range N/A N/A N/A 167.31 334.62 669.25 N/A