DUAL-BAND RF SYNTHESIZER WITH INTEGRATED VCOS FOR WIRELESS COMMUNICATIONS

Si413 3 Si4 123 /2 2/13 /1 2 D U A L -B A N D R F S Y N T H E S I Z E R WI T H I N T E G R A T E D V C O S F O R WI R E L E S S C O M M U N I C A T I O N S Features ! " " RF1: 900 MHz to 1.8 GHz RF2: 750 MHz to 1.5 GHz IF: 62.5 MHz to 1000 MHz ! ! ! ! ! ! ! IF Synthesizer " Integrated VCOs, Loop Filters, ! Varactors, and Resonators Minimal (2) External Components Required S Dual-Band RF Synthesizers ! Low Phase Noise Programmable Power Down Modes 1 µA Standby Current 18 mA Typical Supply Current 2.7 V to 3.6 V Operation Packages: 24-Pin TSSOP, 28-Lead MLP i4 13 Ordering Information: See page 31. Applications ! ! Dual-Band Communications Digital Cellular Telephones GSM, DCS1800, PCS1900 ! ! ! Digital Cordless Phones Analog Cordless Phones Wireless LAN and WAN 3- Pin Assignments B T Si4133-BT SCLK SDA TA GNDR RFLD RFLC GNDR RFLB RFLA GNDR 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 SENB V DDI IFOUT GNDI IFLB IFLA GNDD V DDD GNDD XIN PWDNB A UXOUT Description The Si4133 is a monolithic integrated circuit that performs both IF and dualband RF synthesis for wireless communications applications. The Si4133 includes three VCOs, loop filters, reference and VCO dividers, and phase detectors. Divider and power-down settings are programmable through a three-wire serial interface. Functional Block Diagram GNDR RFOUT V DDR X IN R eference A m plifier P ow er D ow n C ontrol ÷R P hase D etector R F1 R FLA R FLB PW DNB ÷N ÷R R FO UT GNDR Si4133-BM SDA TA SCLK SENB IFOUT GNDI V DDI S D AT A S C LK S E NB S erial Interface 22-bit D ata R egister P hase D etector R F2 R FLC R FLD GNDR 28 1 2 3 4 5 6 7 8 GNDR 27 26 25 24 23 22 21 20 19 18 17 16 15 GNDI IFLB IFLA GNDD V DDD GNDD XIN ÷N RFLD A U XO U T Test Mux ÷R P hase D etector IF RFLC IFD IV IFO U T GNDR RFLB RFLA GNDR ÷N IFLA IFLB 9 GNDR 10 RFOUT 11 V DDR 12 A UXOUT 13 PWDNB 14 GNDD Patents pending Rev. 1.1 3/01 Copyright © 2001 by Silicon Laboratories Si4133-DS11 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. S i4 13 3 2 Rev. 1.1 Si4133 TA B L E O F CON T E N T S Section Page 4 16 16 16 17 17 18 18 19 19 19 20 21 27 29 31 31 32 33 34 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting the VCO Center Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extended Frequency Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self-Tuning Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Loop Dynamics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RF and IF Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Frequency Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auxiliary Output (AUXOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions: Si4133-BT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions: Si4133-BM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Si4133 Derivative Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline: Si4133-BT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline: Si4133-BM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rev. 1.1 3 S i4 13 3 Electrical Specifications Table 1. Recommended Operating Conditions Parameter Ambient Temperature Supply Voltage Supply Voltages Difference Symbol TA VDD V∆ (VDDR – VDDD), (VDDI – VDDD) Test Condition Min –40 2.7 –0.3 Typ 25 3.0 — Max 85 3.6 0.3 Unit °C V V Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25°C unless otherwise stated. Table 2. Absolute Maximum Ratings1,2 Parameter DC Supply Voltage Input Current3 Input Voltage3 Storage Temperature Range Symbol VDD IIN VIN TSTG Value –0.5 to 4.0 ±10 –0.3 to VDD+0.3 –55 to 150 Unit V mA V o C Notes: 1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. This device is a high performance RF integrated circuit with an ESD rating of < 2 kV. Handling and assembly of this device should only be done at ESD-protected workstations. 3. For signals SCLK, SDATA, SENB, PWDNB and XIN. 4 Rev. 1.1 Si4133 Table 3. DC Characteristics (VDD = 2.7 to 3.6 V, TA = –40 to 85°C) Parameter Total Supply Current 1 Symbol Test Condition RF1 and IF operating Min — — — — Typ 18 10 9 8 1 — — — — — — Max 27 16 16 13 — — 0.3 VDD 10 10 — 0.4 Unit mA mA mA mA µA V V µA µA V V RF1 Mode Supply Current1 RF2 Mode Supply Current1 IF Mode Supply Current1 Standby Current High Level Input Voltage2 Low Level Input Voltage2 High Level Input Current2 Low Level Input Current2 High Level Output Voltage3 Low Level Output Voltage3 VIH VIL IIH IIL VOH VOL VIH = 3.6 V, VDD = 3.6 V VIL = 0 V, VDD= 3.6 V IOH = –500 µA IOH = 500 µA PWDNB = 0 — 0.7 VDD — –10 –10 VDD–0.4 — Notes: 1. RF1 = 1.6 GHz, RF2 = 1.1 GHz, IFOUT = 550 MHz, LPWR = 0 2. For signals SCLK, SDATA, SENB, and PWDNB. 3. For signal AUXOUT. Rev. 1.1 5 S i4 13 3 Table 4. Serial Interface Timing (VDD = 2.7 to 3.6 V, TA = –40 to 85°C) Parameter1 SCLK Cycle Time SCLK Rise Time SCLK Fall Time SCLK High Time SCLK Low Time SDATA Setup Time to SCLK↑2 SDATA Hold Time from SCLK↑2 SENB↓ to SCLK↑ Delay Time 2 Symbol tclk tr tf th tl tsu thold ten1 ten2 ten3 tw Test Condition Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Min 40 — — 10 10 5 0 10 12 12 10 Typ — — — — — — — — — — — Max — 50 50 — — — — — — — — Unit ns ns ns ns ns ns ns ns ns ns ns SCLK↑ to SENB↑ Delay Time2 SENB↑ to SCLK↑ Delay Time2 SENB Pulse Width Notes: 1. All timing is referenced to the 50% level of the waveforms unless otherwise noted. 2. Timing is not referenced to 50% level of the waveform. See Figure 2. tr 80% tf S CLK 50% 20% th t clk tl Figure 1. SCLK Timing Diagram 6 Rev. 1.1 Si4133 ts u thold S CLK S DA TA D17 D16 D15 A1 A0 ten3 ten2 ten1 S E NB tw Figure 2. Serial Interface Timing Diagram First bit c loc ked in Las t bit c loc ked in DDDDDDDDD 17 16 15 14 13 12 11 10 9 D 8 D 7 D 6 DD 54 D 3 D 2 D 1 D 0 A 3 A 2 A 1 A 0 data field addres s field Figure 3. Serial Word Format Rev. 1.1 7 S i4 13 3 Table 5. RF and IF Synthesizer Characteristics (VDD = 2.7 to 3.6 V, TA = –40 to 85°C) Parameter1 XIN Input Frequency Reference Amplifier Sensitivity Phase Detector Update Frequency RF1 VCO Center Frequency Range RF1 VCO Tuning Range2 RF2 VCO Center Frequency Range RF Tuning Range from fCEN IF VCO Center Frequency Range IFOUT Tuning Range IFOUT Tuning Range from fCEN RF1 VCO Pushing RF2 VCO Pushing IF VCO Pushing RF1 VCO Pulling RF2 VCO Pulling IF VCO Pulling RF1 Phase Noise RF1 Integrated Phase Error RF2 Phase Noise RF2 Integrated Phase Error IF Phase Noise IF Integrated Phase Error Symbol fREF VREF fφ fCEN Test Condition Min 2 0.5 Typ — — — — — — — — — — 500 400 300 900 300 100 –132 0.9 –134 0.7 –117 0.4 Max 26 VDD +0.3 V 1.0 1720 2050 1429 5 952 1000 5 — — — — — — — — — — — — Unit MHz VP-P MHz MHz MHz MHz % MHz MHz % kHz/V kHz/V kHz/V MHz kHz kHz dBc/Hz degrees rms dBc/Hz degrees rms dBc/Hz degrees rms fφ = fREF/R 0.010 947 Extended frequency operation fCEN Note: LEXT ±10% fCEN with IFDIV Note: LEXT ±10% Open loop 1850 789 –5 526 62.5 –5 — — — VSWR = 2:1, all phases, open loop — — — 1 MHz offset 10 Hz to 100 kHz 1 MHz offset 10 Hz to 100 kHz 100 kHz offset 100 Hz to 100 kHz — — — — — — Notes: 1. fφ = 200 kHz, RF1 = 1.6 GHz, RF2 = 1.2 GHz, IFOUT = 550 MHz, LPWR = 0, for all parameters unless otherwise noted. 2. Extended frequency operation only. VDD ≥ 3.0 V, MLP only, VCO Tuning Range fixed by directly shorting the RFLA and RFLB pins. See Application Note 41 for more details on the Si4133 extended frequency operation. 3. From power up request (PWDNB↑ or SENB↑ during a write of 1 to bits PDIB and PDRB in Register 2) to RF and IF synthesizers ready (settled to within 0.1 ppm frequency error). 4. From power down request (PWDNB↓, or SE