Precision CML Buffer

SY58603U 4.25Gbps Precision CML Buffer with Internal Termination and Fail Safe Input General Description The SY58603U is a 2.5/3.3V, high-speed, fully Precision Edge® differential CML buffer optimized to provide less than Features 10pspp total jitter. The SY58603U can process clock signals as fast as 2.5GHz or data patterns up to • Precision 400mV CML buffer 4.25Gbps. • Guaranteed AC performance over temperature and The differential input includes Micrel’s unique, 3-pin voltage: input termination architecture that interfaces to LVPECL, – DC-to >4.25Gbps throughput LVDS or CML differential signals, (AC-coupled or DC– <300ps propagation delay (IN-to-Q) coupled) as small as 100mV (200mVpp) without any – <85ps rise/fall times level-shifting or termination resistor networks in the • Fail Safe Input signal path. For AC-coupled input interface applications, – Prevents output from oscillating when input is an integrated voltage reference (VREF-AC) is provided to invalid bias the VT pin. The output is 400mV CML, with extremely fast rise/fall times guaranteed to be less than • Ultra-low jitter design 85ps. – <1psRMS cycle-to-cycle jitter The SY58603U operates from a 2.5V ±5% supply or – <10psPP total jitter 3.3V ±10% supply and is guaranteed over the full – <1psRMS random jitter industrial temperature range (–40°C to +85°C). For – <10psPP deterministic jitter applications that require LVPECL or LVDS outputs, www.DataSheet4U.com • High-speed CML output consider the SY58604U and SY58605U, buffers with 800mV and 325mV output swings respectively. The • 2.5V ±5% or 3.3V ±10% power supply operation SY58603U is part of Micrel’s high-speed, Precision • Industrial temperature range: –40°C to +85°C Edge® product line. • Available in 8-pin (2mm x 2mm) MLF® package Data sheets and support documentation can be found on Micrel’s web site at: www.micrel.com. Applications Functional Block Diagram • • • • • Data Distribution: OC-48, OC-48+FEC, XAUI Backplane Buffering SONET clock or data distribution Fibre Channel clock or data distribution Gigabit Ethernet clock or data distribution Markets • • • • • • • Precision Edge is a registered trademark of Micrel, Inc. MLF and MicroLeadFrame are registered trademarks of Amkor Technology Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com Storage ATE Test and measurement Enterprise networking equipment High-end servers Access Metro area network equipment September 2006 M9999-092206-A hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY58603U Ordering Information(1) Part Number SY58603UMG SY58603UMGTR(2) Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only. 2. Tape and Reel. Package Type MLF-8 MLF-8 Operating Range Industrial Industrial Package Marking 603 with Pb-Free bar-line indicator 603 with Pb-Free bar-line indicator Lead Finish NiPdAu Pb-Free NiPdAu Pb-Free Pin Configuration 8-Pin MLF® (MLF-8) Pin Description Pin Number 1, 4 Pin Name IN, /IN Pin Function Differential Input: This input pair is the differential signal input to the device. Input accepts DC-Coupled differential signals as small as 100mV (200mVpp). Each pin of this pair internally terminates with 50Ω to the VT pin. If the input swing falls below a certain threshold (typical 30mV), the Fail Safe Input (FSI) feature will guarantee a stable output by latching the output to its last valid state. See “Input Interface Applications” section for more details. Input Termination Center-Tap: Each side of the differential input pair terminates to VT pin. This pin provides a center-tap to a termination network for maximum interface flexibility. See “Input Interface Applications” section. Reference Voltage: This output biases to VCC–1.2V. It is used for AC-coupling input IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with 0.01µF low ESR capacitor to VCC. Maximum sink/source current is ±1.5mA. Please refer to the “Input Interface Applications” section for more details. Ground: Exposed pad must be connected to a ground plane that is the same potential as the ground pin. CML Differential Output Pair: Differential buffered output copy of the input signal. The output swing is typically 400mV. See “CML Output Termination” section. Positive Power Supply: Bypass with 0.1uF//0.01uF low ESR capacitors as close to the VCC pin as possible. 2 VT 3 VREF-AC 5 6, 7 8 GND Exposed pad /Q, Q VCC September 2006 2 M9999-092206-A hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY58603U Absolute Maximum Ratings(1) Supply Voltage (VCC) ............................... –0.5V to +4.0V Input Voltage (VIN) .......................................–0.5V to VCC CML Output Voltage (VOUT) .......... VCC-1.0V to VCC+0.5V Current (VT) Source or sink on VT pin .............................±100mA Input Current Source or sink Current on (IN, /IN) ................±50mA Current (VREF) Source or sink current on VREF-AC(4) ..............±1.5mA Maximum operating Junction Temperature .......... 125°C Lead Temperature (soldering, 20sec.) .................. 260°C Storage Temperature (Ts) ....................–65°C to +150°C Operating Ratings(2) Supply Voltage (VIN)........................ +2.375V to +3.60V Ambient Temperature (TA) ................... –40°C to +85°C Package Thermal Resistance(3) MLF® Still-air (θJA) ............................................ 93°C/W Junction-to-board (ψJB) .......................... 56°C/W DC Electrical Characteristics(5) TA = –40°C to +85°C, unless otherwise stated. Symbol VCC ICC RDIFF_IN VIH VIL VIN VDIFF_IN VIN_FSI VREF-AC VT_IN Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. ψJB and θJA values are determined for a 4-layer board in still-air number, unless otherwise stated. 4. Due to the limited drive capability, use for input of the same package only. 5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 6. VIN(max) is specified when VT is floating. Parameter Power Supply Voltage Range Power Supply Current Differential Input Resistance (IN-to-/IN) Input HIGH Voltage (IN, /IN) Input LOW Voltage (IN, /IN) Input Voltage Swing (IN, /IN) Differential Input Voltage Swing (|IN - /IN|) Input Voltage Threshold that Triggers FSI Output Reference Voltage Voltage from Input to VT Condition Min 2.375 3.0 Typ 2.5 3.3 39 Max 2.625 3.6 50 110 VCC VIH–0.1 1.7 Units V mA Ω V V V V No load, max. VCC 90 IN, /IN IN, /IN see Figure 3a, Note 6 see Figure 3b 1.2 0 0.1 0.2 100 30 VCC–1.3 VCC–1.2 100 VCC–1.1 1.28 mV V V September 2006 3 M9999-092206-A hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY58603U CML Output DC Electrical Characteristics(7) VCC = +2.5V ±5% or +3.3V ±10%, RL = 100Ω across the outputs; TA = –40°C to +85°C, unless otherwise stated. Symbol VOH VOUT VDIFF_OUT ROUT Note: 7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. Parameter Output HIGH Voltage Output Voltage Swing Differential Output Voltage Swing Output Source Impedance Condition RL = 50Ω to VCC See Figure 3a See Figure 3b Min VCC-0.020 325 650 45 Typ VCC-0.010 400 800 50 Max VCC Units V mV mV 55 Ω September 2006 4 M9999-092206-A hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY58603U AC Electrical Characteristics VCC = +2.5V ±5% or +3.3V ±10%, RL = 100Ω across the outputs, Input tr/tf: <300ps; TA = –40°C to +85°C, unless otherwise stated. Symbol fMAX tPD tSkew tJitter Parameter Maximum Frequency Propagation Delay Part-to-Part Skew Data Clock tr, tf Random Jitter Deterministic Jitter Cycle-to-Cycle Jitter Total Jitter Output Rise/Fall Times (20% to 80%) Duty Cycle Notes: 8. 9. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the respective inputs. Random jitter is measured with a K28.7 pattern, measured at ≤ fMAX. 23 Condition NRZ Data VOUT > 200mV IN-to-Q VIN: 100mV-200mV VIN: 200mV-800mV Note 8 Note 9 Note 10 Note 11 Note 12 At full output swing. Differential I/O Clock Min 4.25 2.5 150 120 Typ 3 250 190 Max Units Gbps GHz 350 300 100 1 10 1 10 ps ps ps psRMS psPP psRMS psPP ps % 30 47 50 85 53 10. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2 –1 PRBS pattern. 11. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. tJITTER_CC = Tn –Tn+1, where T is the time between rising edges of the output signal. 12. Total jitter definition: with an ideal clock input frequency of ≤ fMAX (device), no more than one output edge in 10 output edges will deviate by more than the specified peak-to-peak jitter value. 12 September 2006 5 M9999-092206-A hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY58603U Functional Description Fail-Safe Input (FSI) The input includes a special failsafe circuit to sense the amplitude of the input signal and to latch the output when there is no input signal present, or when the amplitude of the input signal drops sufficiently below 100mVPK (200mVPP), typically 30mVPK. Maximum frequency of SY58603U is limited by the FSI function.