ULTRA-PRECISION DIFFERENTIAL 400MV LVPECL 2:1 MUX

Micrel ULTRA-PRECISION CML DATA AND CLOCK SYNCHRONIZER W/ INTERNAL INPUT AND OUTPUT TERMINATION Precision Edge™ SY58052U Precision Edge™ SY58052U FEATURES s Resynchronizes data to a reference clock s Guaranteed AC performance over temperature and voltage: • DC-to > 10.7Gbps data rate throughput • DC-to > 7GHz clock fMAX • < 190ps Any In-to-Out tpd • tr / tf < 60ps Precision Edge™ DESCRIPTION The SY58052U is an ultra-fast, precision, low jitter datato-clock resynchronizer with a guaranteed maximum data and clock throughput of 10.7Gbps or 7GHz, respectively. The SY58052U is an ideal solution for backplane retiming s Ultra low-jitter design: or retiming after the data passes through long trace lengths. • < 1psrms random jitter Serial data comes into the data input, and the CML output • < 10pspp deterministic jitter is synchronous to the input reference clock’s rising edge. • < 10pspp total jitter (clock) The SY58052U differential inputs include a unique, s Internal 50Ω input termination internal termination design that allows access to the s Unique input termination and VT pin accepts DCtermination network through a VT pin. This feature allows coupled and AC-coupled inputs (CML, PECL) the device to easily interface to different logic standards, both AC- and DC-coupled, without external resistor-bias s Internal 50Ω output source termination and termination networks. The result is a clean, stub-free, s 400mV CML output swing low-jitter interface solution. The differential CML output is s Power supply 2.5V ±5% or 3.3V ±10% optimized for 50Ω environments with internal 50Ω source s –40°C to 85°C temperature range termination and a 400mV output swing. s Available in a 16-pin (3mm × 3mm) MLF™ package The SY58052U operates from a 2.5V or 3.3V supply and www.DataSheet4U.com is guaranteed over the full industrial temperature range APPLICATIONS (–40°C to +85°C). The SY58052U is part of a Micrel’s Precision Edge™ product family. s Data communication systems All support documentation can be found on Micrel’s web s Serial OC-192, OC-192+FEC data-to-clock site at www.micrel.com. realignment s s s s Parallel 10Gbps for OC768 All SONET OC-3 — OC-768 applications All Fibre Channel applications All GigE applications FUNCTIONAL BLOCK DIAGRAM DATA 50Ω VTD 50Ω /DATA CLK 50Ω VTCLK 50Ω /CLK /CLK R CLK DATA /DATA TYPICAL APPLICATION SY58052U Data from Backplane (Uncertain timing) DATA Q /Q Q /Q Clock from Backplane CLK Q Retimed Data DATA IN CLK /RESET Q OUT (Retimed) Precision Edge is a trademark of Micrel, Inc. and AnyGate is a registered trademark of Micrel, Inc. MicroLeadFrame and MLF are trademarks of Amkor Technology, Inc. M9999-050404 hbwhelp@micrel.com or (408) 955-1690 Rev.: A Amendment: /0 1 Issue Date: May 2004 Micrel Precision Edge™ SY58052U PACKAGE/ORDERING INFORMATION VTCLK GND GND VCC Ordering Information(1) Part Number Package Type DIE MLF-16 MLF-16 Operating Range Ambient Industrial Industrial Package Marking — 052U 052U 16 15 14 13 CLK /CLK DATA /DATA 1 2 3 4 5678 VTDATA /RESET GND VCC 12 11 10 9 Q GND GND /Q SY58052UMI SY58052UMI SY58052UMITR(2) Notes: 1. Contact factory for die availability. Die is guaranteed at TA = 25°C, DC electricals only. 2. Tape and Reel. 16-Pin MLF™ (MLF-16) PIN DESCRIPTION Pin Number 1, 2 Pin Name CLK, /CLK Pin Function Differential Input: This input pair is the clock signal that re-times the data signal at DATA, /DATA. Each pin of this pair internally terminates to the VTCLK pin to 50Ω. Note that this input will default to an indeterminate state if left open. See “Input Interface Applications” section. Differential Input: This input pair is the signal to be synchronized by the CLK, /CLK signal. Each pin of this pair internally terminates to the VTD pin to 50Ω. Note that this input will default to an indeterminate state if left open. See “Input Interface Applications” section. Input Termination Center-Tap: Each of the two inputs, DATA, /DATA terminates to this pin. The VTData pin provides a center-tap to a termination network for maximum interface flexibility. See “Input Interface Applications” section. TTL/CMOS-Compatible Input: The /RESET input asynchronously forces the Q output to a logic “0” state whenever it is active low. Possible state changes due to rising edges on CLK, /CLK are ignored until /RESET goes inactive high. Ground. Exposed pad must be connected to the same potential as the GND pin. Positive Power Supply. Bypass with 0.1µF0.01µF low ESR capacitors. Differential Output: This CML output pair is the output of the flip-flop. The Data input is transferred to the Q output at the rising edge of CLK (falling edge of /CLK). See “Input Interface Applications” section. Input Termination Center-Tap: Each of the two inputs, CLK, /CLK terminates to this pin. The VTCLK pin provides a center-tap to a termination network for maximum interface flexibility. See “Input Interface Applications” section. 3, 4 DATA, /DATA 5 VTData 6 /RESET 7, 10, 11, 14, 15 8, 13 12, 9 GND (Exposed Pad) VCC Q, /Q 16 VTCLK TRUTH TABLES DATA X X X 0 1 /DATA X X X 1 0 CLK X 0 1 /CLK X 1 0 /RESET 0 1 1 1 1 Q 0 QN–1 QN–1 0 1 /Q 1 /QN–1 /QN–1 1 0 M9999-050404 hbwhelp@micrel.com or (408) 955-1690 2 Micrel Precision Edge™ SY58052U Absolute Maximum Ratings(1) Supply Voltage (VCC) .................................. –0.5V to +4.0V Input Voltage (VIN) ......................................... –0.5V to VCC CML Output Voltage (VOUT) ......... VCC –1.0V to VCC +5.0V Termination Current(3) Source or Sink Current on VTD, VCLK ....................... ±60mA Input Current Source or Sink Current on D, /D, CLK, /CLK ....... ±30mA Lead Temperature (soldering, 10 sec.) ................... +265°C Storage Temperature (TS) ....................... –65°C to +150°C Operating Ratings(2) Supply Voltage (VCC) .......................... +2.375V to +2.625V ............................................................ +3.0V to +3.6V Ambient Temperature (TA) ......................... –40°C to +85°C Package Thermal Resistance(4) MLF™ (θJA) Still-Air ............................................................. 61°C/W MLF™ (ψJB) Junction-to-Board ............................................ 38°C/W DC ELECTRICAL CHARACTERISTICS(5) TA = –40°C to +85°C, unless otherwise noted. Symbol VCC ICC RIN VIH VIL VIN VDIFF_IN |IIN| Notes: 1. Permanent device damage may occur if the ratings in the “Absolute Maximum Ratings” section are exceeded. This is a stress rating only and functional operation is not implied for conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Due to the limited drive capability use for input of the same package only. 4. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device’s most negative potential on the PCB. ψJB uses 4-layer θJA in still-air, unless otherwise stated. 5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 6. Due to the internal termination (see “ Input Structures” section) the input current depends on the applied voltages at D, /D and VTD inputs, the CLK, /CLK and VTCLK inputs or the S, /S and VTS inputs. Do not apply a combination of voltages that causes the input current to exceed the maximum limit! Parameter Power Supply Power Supply Current Differential Input Resistance (D, /D or CLK, /CLK) Input HIGH Voltage (D, /D or CLK, /CLK) Input LOW Voltage (D, /D or CLK, /CLK) Input Voltage Swing (D, /D or CLK, /CLK) Differential Input Voltage Swing |D, /D| or |CLK, /CLK| Input Current (IN, /IN) Condition Min 2.375 3.0 Typ Max 2.625 3.6 Units V V mA Ω V V mV mV No load, max. VCC. 80 Note 6 Note 6 Note 6 Note 6 See Figure 2a. Note 6 See Figure 2b. 1.2 0 100 200 60 100 90 120 VCC VIH–0.1 21 mA M9999-050404 hbwhelp@micrel.com or (408) 955-1690 3 Micrel Precision Edge™ SY58052U LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS(7) VCC = 2.5V ±5% or 3.3V ±10%; TA = –40°C to +85°C; unless otherwise noted. Symbol VIH VIL IIH IIL Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current –125 Condition Min 2.0 0.8 20 –300 Typ Max Units V mV µA µA CML OUTPUTS DC ELECTRICAL CHARACTERISTICS(7) VCC = 2.5V ±5% or 3.3V ±10%; RL = 100Ω across output pair or equivalent; TA = –40°C to +85°C; unless otherwise noted. Symbol VOH VOUT VDIFF_OUT ROUT Parameter Output HIGH Voltage Q, /Q Output Voltage Swing Q, /Q Differential Output Voltage Swing Q, /Q Output Source Impedance Q, /Q See Figure 2a. See Figure 2b. Condition Min VCC–0.020 325 650 40 400 800 50 Typ Max VCC 500 1000 60 Units V mV mV Ω AC ELECTRICAL CHARACTERISTICS(8) VCC = 2.5V ±5% or 3.3V ±10%; RL = 100Ω across output pair or equivalent; TA = –40°C to +85°C; unless otherwise noted. Symbol fMAX tpd tRESET tS tH tRR tJITTER Parameter Maximum Operating Frequency Propagation Delay Propagation Delay (RESET-to-Q) Set-Up Time Hold Time Reset Recovery Time Random Jitter (RJ) Deterministic Jitter (DJ) Total Jitter (TJ) tr, tf Notes: 7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 8. Measured with 100mV input swing. See “Timing Diagrams” section for definition of parameters. High-frequency AC-parameters are guaranteed by design and characterization. 9. RJ is measured with a K28.7 comma detect character pattern, measured at 10.7Gbps and 2.5Gbps. 10. DJ is measured at 10.7Gbps and 2.5Gbps, with both K28.5 and 223–1 PRBS pattern 11. Total jitter definition: with an ideal clock input frequency of ≤ fMAX, no mo